Principal Advanced Packaging Design Engineer (AI)

Location: Burlington, Vermont, United States. The role may involve access to export-controlled technology and software under U.S. export regulations; applicants may be subject to an export license review.

Expected base pay: $168,400–$249,310 per annum, plus eligibility for bonus and equity plans.

Company

hirify.global develops semiconductor solutions for enterprise, cloud and AI, carrier, and data-infrastructure applications.

What you will do

• Lead small teams of design and simulation engineers delivering advanced packaging solutions.
• Drive package definition and architecture development for performance-line products and thermal-mechanical development vehicles.
• Develop multi-chip and multi-component 2.5D and 3D package solutions, including advanced substrates and co-packaged copper or optical technologies.
• Work with package suppliers to select technologies and ensure manufacturability, performance, reliability, and cost targets.
• Collaborate with internal stakeholders, external partners, customers, chip design teams, and electrical simulation teams.

Requirements

• 15+ years of relevant experience with a bachelor's degree, 12+ years with a master's degree, or 8+ years with a Ph.D. in Electrical Engineering or a related field.
• Extensive experience in substrate or board design for advanced packaging technologies.
• Strong knowledge of design-for-manufacturing, reliability, signal integrity, power integrity, and thermal-mechanical development.
• Experience leading complex package architecture and design-for-manufacturing projects involving cross-functional stakeholders and external partners.
• Expertise with Cadence 3DIC, ISP, APD, and SiP workflows.
• Applicants must be eligible to access export-controlled information under applicable U.S. regulations; export license review may be required.

Nice to have

• Experience with HBM, DDR, SerDes, D2D, D2H, ADC, DAC, PCIe, Ethernet, and related technologies.
• Knowledge of CoWoS-S/R/L, EMIB, CPO, and CPC packaging technologies.
• Familiarity with Cadence Sigrity, Clarity, Innovus, Virtuoso, Ansys, AutoCAD, and SolidWorks.
• Experience with signal and power integrity simulations, tool and workflow development, and library maintenance.

Culture & Benefits

• Work with global stakeholders across multiple time zones on advanced semiconductor packaging technologies.
• Eligible for bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
• Benefits support financial well-being, family support, mental and physical health, and recognition.
• Additional benefits include an employee stock purchase plan, family support programs, mental health resources, and service awards.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills.
• AI tools, transcription apps, automated note-taking bots, and real-time answer generators are prohibited during interviews.