ADCE Packaging Design Architect (Semiconductor)

TL;DR

ADCE Packaging Design Architect (Semiconductor): Driving end-to-end substrate design development from concept through tape-out with an accent on physical layout, routing, and performance optimization. Focus on establishing design, performance, and cost tradeoffs while collaborating with silicon and hardware teams to ensure optimal system-level integration.

Location: Must be based in the US (On-site presence required)

Salary: $220,920–$311,890 USD

Company

hirify.global is a global leader in semiconductor manufacturing, delivering cutting-edge silicon process and packaging technology for the AI era.

What you will do

• Drive end-to-end substrate design development from initial concept to final tape-out.
• Perform substrate fit and routing studies to balance design, performance, and cost requirements.
• Collaborate with silicon and hardware teams to optimize silicon-package-board performance and pinout.
• Define substrate design rules and conduct comprehensive internal and external design reviews.
• Analyze data and resolve Design Rule Checks (DRCs) to ensure high-quality package design.
• Manage documentation and collateral within the product lifecycle management system.

Requirements

• Ph.D. or Master’s degree in Electrical, Chemical, or Mechanical Engineering, or Material Science.
• 10+ years of in-depth experience in Package, PCB design, or IC digital design.
• Strong background in semiconductor fabrication and packaging processes.
• Proficiency with design and electromagnetic simulation tools such as Mentor, Cadence, SPICE, and Ansys.
• Expertise in Cadence Allegro (APD/SiP, Concept HDL, Sigrity) or Mentor Xpedition platforms.
• Must be able to work on-site at designated US hirify.global locations.

Nice to have

• Knowledge of assembly process, test, and characterization techniques.
• Experience working independently across various levels of design abstraction.

Culture & Benefits

• Competitive total compensation package including base pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Opportunity to work on state-of-the-art semiconductor manufacturing technology.
• Collaborative environment within a worldwide factory network.