ADCE Packaging Design Architect (Semiconductor Packaging)

Location: On-site in the United States, with primary location in Phoenix, Arizona and additional locations in Folsom and Santa Clara, California; Fort Collins, Colorado; Beaver Brook, Massachusetts; Albuquerque, New Mexico; Hillsboro, Oregon; Austin, Texas; and multiple cities in Washington.

Annual salary: $220,920–$311,890 USD

Company

hirify.global develops semiconductor technologies and hardware products.

What you will do

• Drive substrate design from concept through tape out and implement package layout and routing.
• Perform substrate fit and routing studies to evaluate design, performance, and cost tradeoffs.
• Collaborate with silicon and hardware teams to optimize silicon-package-board performance and pinout.
• Define substrate design rules and conduct internal and external design reviews.
• Analyze data, resolve design-rule checks, and optimize package designs.
• Complete design documentation and lifecycle-management collateral.

Requirements

• Master’s or Ph.D. in electrical, chemical, or mechanical engineering, or materials science.
• 10+ years of experience with package design, PCB design, or IC digital design.
• Strong technical background in design and electrical analysis, with experience in semiconductor fabrication and packaging.
• Experience with design and electromagnetic simulation tools such as Mentor, Cadence, SPICE, and Ansys.
• Experience with Cadence Allegro platform tools and/or Mentor Xpedition platform tools.
• Strong analytical, problem-solving, organizational, communication, and independent-working skills.

Nice to have

• Experience and knowledge of assembly processes, testing, and characterization techniques.

Culture & Benefits

• Full-time experienced-hire position.
• On-site work model with Shift 1 in the United States.
• Competitive pay and stock bonuses.
• Health, retirement, and vacation benefits.
• Position of Trust requiring an extended background investigation, subject to applicable law.