Layout Scale-Up Engineer (Quantum Hardware)

Location: Paris, France; hybrid workplace with a flexible remote policy of up to 40% per month.

Company

Alice & Bob is a French early-stage startup developing a fault-tolerant universal quantum computer based on superconducting Schrödinger cat qubits.

What you will do

• Build and own the PDK, including the layer stack, technology files, parametric cells, and DRC/LVS decks.
• Design tile-based hierarchical layout methodologies for wafer-scale and multi-chip designs.
• Develop Python, GDS, or vendor-EDA-scripted generators that produce DRC-clean GDSII/OASIS layouts without manual drawing.
• Own mask generation from floorplanning and hierarchical layout through verification, wafer mapping, test structures, and tape-out data preparation.
• Drive automated-layout targets and keep DRC/LVS/PEX runtime and file sizes manageable at very large element counts.
• Evaluate EDA tools, integrate electromagnetic-simulation handoff, and provide physical-implementation signoff before mask release.

Requirements

• 5+ years of experience in physical design, custom or analog layout, PDK development, or semiconductor mask data preparation.
• At least one production tape-out owned end-to-end.
• Experience replacing hand-drawn layout with generators, PCells, or hierarchical flows.
• Hands-on parasitic extraction experience, including deck or rule-file development and correlation with electromagnetic simulation or measurements.
• Strong layout-automation scripting with Python and/or vendor languages such as SKILL or Tcl.
• Fluency in DRC/LVS deck authoring, GDSII/OASIS, reticle and stepper constraints, tape-out data preparation, and converting frequency or floorplan constraints into geometry.

Nice to have

• Experience with superconducting or cryogenic device layout, including thin films, Josephson junctions, CPW resonators, and airbridges.

Culture & Benefits

• Opportunity to work on superconducting quantum-computing hardware with a diverse team spanning more than 35 countries.
• BSPCE plan and additional intellectual-property compensation for core quantum-architecture patents.
• 25 days of vacation plus RTT, French-law transportation support, meal vouchers, and health coverage.
• Parental support, mental-health support, subsidized sports membership, and a stocked office kitchen.
• French-language courses are covered by the company.

Hiring process

• Screening call followed by a hiring-manager interview.
• Technical interview and team presentation, followed by leadership and fit interviews.
• Reference check.