Lead Software Engineer - Low-Power Verification

Location: San Jose, California, United States

Annual salary: $114,800–$213,200, plus potential bonus, equity, and benefits.

Company

hirify.global develops electronic design automation software and emulation and prototyping platforms.

What you will do

• Improve UPF compilation performance, reduce instrumented capacity, and add self-checks across Parallel Partition Compiler and Modular Compiler flows.
• Extend Dielet UPF support and contribute to low-power verification across Palladium and Protium platforms.
• Rebuild UPF documentation around end-to-end compilation workflows using valid SystemVerilog and UPF examples.
• Maintain synchronization between code and documentation through example-driven checks.
• Collaborate with R&D, PE, and AE teams to deploy UPF solutions across AVIP, UVMA, MC, and Dielet flows.
• Help consolidate and unify UPF compilation across Palladium and Protium.

Requirements

• BS in Computer Science, Electrical Engineering, or a related field with 4+ years of experience; MS with 2+ years; PhD with 1+ year; or equivalent practical experience.
• Working knowledge of IEEE 1801 UPF and RTL languages including Verilog, SystemVerilog, and VHDL.
• Ability to read, review, and reason about C++ code and object-oriented designs.
• Scripting experience with Perl, Tcl/Tk, and/or Python.
• Fluency with AI-assisted coding tools such as Copilot, Claude, or Cursor, including critical evaluation of generated output.
• Strong technical writing skills for user guides, specifications, and workflow-focused documentation.

Culture & Benefits

• Paid vacation and paid holidays.
• 401(k) plan with employer match.
• Employee stock purchase plan.
• Medical, dental, and vision plan options.
• Potential eligibility for incentive compensation, including bonus and equity.