Senior Design Automation Engineer - Front End Design Verification (FPGA)

Location: San Jose, California, United States

Salary: $187,900–$270,700 USD annually for the Bay Area, plus incentive opportunities.

Company

FPGA solutions provider developing programmable technologies for AI, cloud, networking, and edge markets.

What you will do

• Develop, deploy, and support design automation flows and methodologies for digital semiconductor design.
• Build scripts, tooling customizations, automation frameworks, and data-driven systems using AI-enabled capabilities.
• Evaluate, integrate, and enhance EDA tools for front-end design and verification workflows.
• Automate repetitive design tasks with robust, scalable, and maintainable solutions.
• Collaborate with design and verification teams to identify bottlenecks and improve workflows.
• Work with internal teams and external EDA vendors to resolve tool issues and adopt new capabilities.

Requirements

• Bachelor’s or Master’s degree in Computer Science, Electrical Engineering, or a related field.
• 8+ years of relevant industry experience with front-end RTL, design verification EDA tools, and FPGA or ASIC design flows.
• Hands-on experience with tools such as VCS, Xcelium, or SpyGlass.
• Experience with AI/ML-driven EDA features or with data pipelines and training systems for learning-based design automation.
• Proficiency in Unix/Linux and Python, Tcl, or Shell, plus experience building automation tools for complex design pipelines.
• Ability to collaborate across functions and translate user requirements into scalable solutions.

Nice to have

• 10+ years of experience with design automation tools.
• Experience with front-end pre-silicon design verification flows and advanced EDA features such as Lint, CDC, or RDC.
• Experience in large-scale SoC or IP development environments.
• Strong communication and collaboration skills across design and CAD/EDA teams.

Culture & Benefits

• Regular full-time employment.
• Incentive opportunities based on individual and company performance.
• Work within a design methodology, automation, and infrastructure team supporting FPGA development.
• Shift 1 schedule in the United States.
• Use of AI in applicant screening, assessment, or selection.