Назад
Company hidden
6 дней назад

Yield Development Engineer (Semiconductor)

Формат работы
onsite
Тип работы
fulltime
Грейд
middle
Английский
b2
Страна
Malaysia
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Yield Development Engineer (Semiconductor): Driving semiconductor manufacturing yield improvements through statistical analysis, failure isolation, process development, and cross-functional debugging with an accent on advanced logic nodes, ATE data correlation, and manufacturability. Focus on analyzing yield limiters, developing high-volume data tools and yield models, and solving complex logic and memory failures from silicon bring-up through production.

Location: Penang, Malaysia; on-site presence required

Company

hirify.global's Foundry team develops high-performance semiconductor solutions and advances process technology and manufacturing capabilities.

What you will do

  • Identify yield limiters using statistical techniques, big data methodologies, and diverse manufacturing data sources.
  • Develop process roadmaps, measurement recipes, and equipment capabilities for advanced logic nodes.
  • Perform fault isolation, failure analysis, and root-cause investigations for logic and memory/array failures.
  • Correlate ATE test results with design and process data while debugging issues from silicon bring-up through production.
  • Execute new product introductions, design-technology co-optimization, and factory experiments to improve yield and manufacturability.
  • Create tools, algorithms, and systems for high-volume data analysis and yield modeling while collaborating with design, test, process, and layout teams.

Requirements

  • Bachelor's degree in electronic engineering, computer engineering, or a related field.
  • 3+ years of experience in semiconductor failure analysis or test engineering.
  • Strong understanding of array architecture and failure mechanisms, or hands-on experience with SCAN ATPG methodology, scan-chain diagnosis, pattern generation, and debug.
  • Experience with fault isolation, electrical fault isolation, circuit and layout analysis, failure signatures, and yield learning.
  • Experience with tester platforms such as Advantest or Teradyne and understanding of DFT concepts and implementation.
  • Strong analytical, problem-solving, communication, and cross-functional collaboration skills.

Nice to have

  • Experience with embedded memory compilers, array redundancy analysis, and BIST for memory and logic.
  • Familiarity with JMP, Python, or R for statistical data analysis.
  • Experience with 7nm, 5nm, 3nm, or smaller process nodes.
  • Exposure to machine-learning-based fault classification or yield analysis.

Culture & Benefits

  • Full-time experienced-hire position on Shift 1 in Malaysia.
  • Cross-functional work across design, process, test, layout, and manufacturing organizations.
  • Focus on technical excellence, collaboration, responsible business practices, and ethical hiring.
  • No recruitment, medical examination, or other hiring fees are charged to candidates.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →