Principal/Sr Principal Digital Design Engineer (AI)

Location: Taipei, Taiwan

Company

hirify.global develops rack-scale AI infrastructure and semiconductor-based connectivity solutions integrating CXL, Ethernet, NVLink, PCIe, and UALink technologies with software for scalable systems.

What you will do

• Define micro-architectures and implement complex digital blocks and subsystems using RTL.
• Optimize power, performance, and area for silicon technologies at or below 7nm.
• Drive timing closure, DFT implementation, production readiness, and design quality.
• Collaborate with verification, physical design, DFT, and post-silicon teams through sign-off and silicon bring-up.
• Integrate third-party IP, develop verification plans, close coverage, and debug complex issues.
• Mentor engineers and improve silicon development methodologies and CAD automation.

Requirements

• Bachelor’s degree in Electrical Engineering or an equivalent field.
• 10+ years of hands-on experience developing complex SoC or silicon products in server, storage, or networking markets.
• Expertise in architecture definition, micro-architecture, RTL coding, functional simulation, and synthesis.
• Strong knowledge of timing closure, gate-level simulation, and DFT implementation.
• Deep expertise in at least one high-speed protocol, such as PCIe, CXL, Ethernet, or DDR.
• Production experience with advanced CMOS nodes at or below 7nm and proficiency with Cadence or Synopsys digital design flows.

Nice to have

• Master’s degree in Electrical Engineering or a related field.
• Experience delivering multiple high-performance designs to production in data-center environments.
• Experience collaborating with embedded firmware teams and familiarity with RISC-V, Arm, or similar processor subsystems.
• Contributions to design methodology, CAD automation, or design infrastructure.

Culture & Benefits

• Opportunity to work on AI infrastructure and high-performance connectivity products used by hyperscalers.
• Collaborative environment involving design, verification, physical design, DFT, firmware, and post-silicon teams.
• Role may be eligible for discretionary bonuses, incentives, and benefits.
• Applications are encouraged from candidates with diverse backgrounds and experiences.