Senior Digital Design Engineer (PCIe/Ethernet)

Location: Toronto, Ontario, Canada. Candidates must be authorized to work in Canada.

Salary: CAD 139,500–155,000, depending on experience, level, and business need. The role may also be eligible for discretionary bonuses, incentives, and benefits.

Company

hirify.global provides rack-scale AI infrastructure through connectivity solutions based on CXL, Ethernet, NVLink, PCIe, UALink, and its COSMOS software suite.

What you will do

• Develop micro-architectures and synthesizable RTL for PCIe and Ethernet controllers, bridges, switches, and SerDes-related IP.
• Own block-level and full-chip design deliverables from specification through implementation and GDS handoff.
• Integrate controller, SerDes, processor, peripheral, and other IP with RTL, physical design, DFT, verification, and firmware teams.
• Drive synthesis, timing analysis and closure, clock-domain crossing, lint, gate-level simulation, emulation, and design-quality reviews.
• Contribute to top-level integration, floor planning, PAD planning, DFT implementation, and advanced-process-node designs.
• Collaborate across verification, systems, firmware, and embedded software teams to debug issues and validate hardware-software interfaces.

Requirements

• Bachelor’s degree in Electrical Engineering, Electronics Engineering, or a related field.
• 2–5 years of experience in digital design and implementation for complex SoC or silicon products.
• Hands-on experience with SystemVerilog or Verilog, synthesis, and timing closure.
• Experience with PCIe or Ethernet controllers, bridges, switches, PCS, PHY, SerDes design, or IP integration.
• Experience with front-end design, gate-level simulation, clock-domain crossing, lint, or related design-quality methodologies.
• Experience using Python or Perl for design, integration, or analysis automation, plus the ability to collaborate across hardware and software teams.

Nice to have

• Experience with PCIe Gen 6/7, UALink, UCI, or high-performance Ethernet SerDes IP.
• Experience with block-level and full-chip implementation at process nodes of 16 nm or smaller.
• Knowledge of PAD design, DFT, floor planning, top-level integration, FPGA prototyping, emulation, or post-silicon debug.
• Experience with NIC, switch, storage, or other high-performance connectivity products and embedded firmware interaction.
• Familiarity with continuous integration and continuous delivery workflows for design and verification.

Culture & Benefits

• Work on connectivity silicon for next-generation rack-scale AI systems.
• Collaborate with hyperscalers, ecosystem partners, and cross-functional engineering teams.
• Contribute to products connecting CPUs, GPUs, memory, storage, and networking devices.
• Discretionary bonus, incentives, and benefits may be available.
• The hiring approach encourages applications from people with diverse backgrounds and experiences.