Senior/Staff Mid-End Engineer (STA/Synthesis) (ASIC)

Location: Malaysia / Singapore

Company

hirify.global develops Bitcoin mining and AI cloud technologies, including ASIC chips, mining rigs, and high-performance computing datacenters.

What you will do

• Perform logic synthesis and optimize ASIC designs.
• Conduct static timing analysis, tune constraints, perform clock tree synthesis, and close timing across multi-clock domains and high-frequency data pipelines.
• Apply low-power techniques such as clock gating, power gating, and dynamic voltage scaling, while optimizing memory hierarchies.
• Collaborate with DFT and physical design teams on scan insertion, MBIST, JTAG, floorplanning, place and route, congestion analysis, and timing bottlenecks.
• Define design constraints for high-speed interconnects, NoCs, and large-scale data movement.
• Debug synthesis, timing, and power issues and verify synthesized netlist correctness using formal verification tools.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3–7 years of IC design experience focused on synthesis, timing closure, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools including Synopsys Design Compiler, Cadence Genus, PrimeTime, and Innovus.
• Strong understanding of timing analysis, multi-clock domain handling, and clock tree synthesis.
• Familiarity with AXI, NoC, mesh, and torus on-chip interconnect architectures.
• Experience with UPF, power gating, dynamic voltage scaling, and scripting in TCL, Python, Perl, or Shell.

Culture & Benefits

• Inclusive environment that values authenticity and diverse perspectives.
• Opportunities to contribute directly to digital asset and AI cloud projects.
• Autonomy, personal accountability, and exposure to new projects and systems.
• Training, mentoring, welfare benefits, and professional development opportunities.