Senior QPU Design Engineer (Quantum Computing)

Location: Oxford, England, United Kingdom; hybrid, three days per week in the Oxford office

Company

hirify.global develops integrated quantum computing, networking, sensing, and security solutions, including ion-trapping quantum processing systems.

What you will do

• Translate operational requirements into chip features, layouts, and design specifications.
• Guide chips through the full design process from requirements to layout and tape-out.
• Lay out complex multi-layer chips, including metal-track routing and interfaces with photonics and CMOS.
• Collaborate with scientists and engineering teams to define specifications, feasibility, and compatibility.
• Independently lead projects and own delivery of final tape-outs.

Requirements

• Senior-level experience translating design requirements into chip features.
• Hands-on experience with complex, multi-layer chip layout, metal-track routing, and photonics and CMOS interfaces.
• Experience guiding chip designs from requirements through layout and tape-out.
• Ability to collaborate across technical teams, solve design problems, and take responsibility for delivery.
• Ability to work from the Oxford office three days per week in a hybrid setup.

Nice to have

• Scripted layout generation using GDSFactory in Python or a similar tool.
• Experience with Cadence for IC layout.
• Experience in ion-trap design, photonics design, or IC packaging.

Culture & Benefits

• Medical, dental, and vision plans.
• Matching 401(k), unlimited PTO, and paid holidays.
• Parental and adoption leave.
• Legal insurance and a home technology stipend.
• Work culture focused on autonomy, productivity, respect, and equal opportunity.