Principal FPGA Emulation Engineer

Location: Austin, TX, USA; onsite role with no remote work available

Company

hirify.global is an embedded semiconductor solution provider developing technology for automotive, industrial, infrastructure, and IoT applications.

What you will do

• Build and own FPGA-based emulation platforms for mixed-signal power ASICs before silicon.
• Work with silicon RTL and DSP architects to adapt ASIC RTL and bring designs onto FPGA while preserving functional equivalence.
• Map large designs onto FPGA resources, optimizing memory, DSP slices, clocking, pipelining, timing, and emulation speed.
• Develop real-time environments for digital cores, including ADC/DAC/PWM interfaces, gate drivers, plant and converter models, and hardware-in-the-loop setups.
• Implement pre-silicon debug and visibility using logic analysis, waveform capture, triggering, assertions, and firmware/software co-development.
• Define emulation methodology, FPGA-ability guidelines, automation flows, and tooling while mentoring engineers and leading technical decisions.

Requirements

• Typically 10+ years of FPGA design and implementation experience, including FPGA prototyping or ASIC/SoC emulation.
• Expert RTL design skills in SystemVerilog and/or VHDL, with experience working from ASIC-style RTL.
• Deep knowledge of FPGA architecture and primitives, including DSP slices, block and distributed RAM, carry chains, clocking, control sets, and fanout management.
• Experience with ASIC-to-FPGA adaptation, clock-gating conversion, memory macro replacement, reset schemes, tri-state conversion, and multi-clock/CDC handling.
• Strong command of synthesis, place-and-route, timing analysis, constraints, and large Xilinx and/or Intel devices using Vivado and/or Quartus.
• Experience with hardware bring-up, ILA/SignalTap, lab instrumentation, TCL/Python automation, technical leadership, and a BS or MS in engineering or equivalent experience.

Nice to have

• Real-time hardware-in-the-loop modeling of analog, mixed-signal, and power stages, including converter control loops, PWM/PFM, and magnetics.
• FPGA DSP implementation involving FIR/IIR/CIC filters, interpolation/decimation, FFT, FEC, and high-throughput folding or unfolding.
• Experience with HAPS, Protium, Veloce, Simulink, Xilinx System Generator, or high-speed interfaces such as JESD204B, PCIe, Ethernet, and Aurora.
• ASIC tape-out, DFT/scan, custom FPGA prototyping platforms, high-speed PCB design, embedded firmware, C/C++, MATLAB, or assembly experience.

Culture & Benefits

• Collaborative work across silicon, systems, RTL, DSP, firmware, and software teams.
• TAGIE culture focused on being Transparent, Agile, Global, Innovative, and Entrepreneurial.
• Opportunity to contribute to semiconductor technology used across automotive, industrial, infrastructure, and IoT markets.
• Competitive employee benefits package provided alongside salary.
• Work is subject to U.S. export-control requirements for dual-use technology.