Senior Design Verification Engineer (RISC-V Vector)

Location: Austin, Texas, United States. Right to work in the United States is required; employment eligibility and export-control authorization are subject to verification.

Company

hirify.global develops high-performance RISC-V compute platforms and processor technologies for applications including artificial intelligence, automotive, data centers, mobile, and consumer products.

What you will do

• Own verification planning and execution for high-performance CPU core areas from block level through core-level integration.
• Create verification strategies, test plans, environments, checkers, scoreboards, assertions, stimulus, and coverage models.
• Develop directed and constrained-random tests for branch prediction, instruction fetch, pipeline interactions, issue and dispatch, hazards, memory ordering, prefetching, and vector execution.
• Drive verification of RISC-V Vector Extension functionality, including arithmetic, memory operations, masking, configuration-dependent execution, exceptions, and scalar-vector interactions.
• Analyze failures, identify root causes, and coordinate fixes across RTL, verification infrastructure, assertions, and test content.
• Collaborate with architecture, RTL, performance, and verification teams to resolve specification ambiguities, close coverage gaps, and achieve signoff quality.

Requirements

• 5+ years of relevant IP, CPU/core, or SoC functional verification experience.
• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Strong hands-on experience with SystemVerilog-based verification methodologies.
• Solid understanding of computer architecture and CPU microarchitecture.
• Experience with test planning, verification environment development, stimulus generation, failure analysis, coverage analysis, and coverage closure.
• Strong programming, scripting, and technical debugging skills, plus experience in at least one CPU core area such as the frontend, midcore, load-store unit, memory ordering, hardware prefetch, or vector unit.

Nice to have

• High-performance out-of-order CPU core verification experience.
• RISC-V Vector Extension, SIMD, or vector-processor verification experience.
• Experience with vector arithmetic, masking, reductions, permutations, vector-scalar operations, and vector load/store behavior.
• Experience with concurrency, replay, flush, redirects, dependency handling, weak memory ordering, formal verification, emulation, or acceleration.
• Experience collaborating with performance, compiler, system verification, and software teams.

Culture & Benefits

• Collaborative work across architecture, RTL, performance, verification, compiler, system verification, and software teams.
• Opportunity to contribute reusable verification methodology, automation, and infrastructure for future CPU generations.
• Comprehensive benefits package that may include healthcare, retirement plans, and paid time off.
• Potential eligibility for variable or incentive compensation and equity.