Principal Silicon Design Engineer (PCIe)

Location: San Jose, California, United States

Salary: $209,500–$303,250 USD per year for the Bay Area California market

Company

hirify.global develops next-generation FPGA platforms and advanced high-speed interface IP.

What you will do

• Lead the architecture and RTL design of complex high-speed interface IP and subsystems, primarily focused on PCIe.
• Define PCIe MAC, PCS, link, subsystem, initialization, equalization, lane-management, and control logic.
• Own designs from architecture and microarchitecture through RTL implementation, verification, synthesis, timing analysis, and silicon validation.
• Integrate digital interfaces with PHY and analog IP, including calibration, equalization, and system-level performance requirements.
• Drive high-speed equalization and signal-processing design involving Tx FFE, Rx FFE, CDR, DFE, LMS, and related methods.
• Provide technical direction across architecture, design reviews, verification, implementation, validation, and engineering collaboration.

Requirements

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
• 12+ years of experience in ASIC, SoC, FPGA, silicon, or digital IC design.
• 8+ years of hands-on RTL development using Verilog and/or SystemVerilog for high-speed interface IP or digital subsystems.
• 5+ years of experience with PCI Express, PCIe PHY/PCS, MAC, Link, or related high-speed serial technologies.
• Experience with digital implementation and signoff, including lint, CDC, synthesis, static timing analysis, and/or equivalence checking.
• Applicants must be eligible for any required U.S. export authorizations.

Nice to have

• Master's degree or Ph.D. in a related technical field.
• Experience with PCIe Gen5/Gen6, PAM4, MATLAB/Simulink, formal verification, SVA, FPGA prototyping, testchips, post-silicon validation, or ATE.
• Experience integrating digital logic with analog PHY IP, including PLL, CDR, DFE, and equalization circuitry.

Culture & Benefits

• Cross-functional collaboration with architecture, analog/PHY, verification, FPGA, software, system, and product engineering teams.
• Opportunities to mentor engineers and influence high-speed interface methodologies, verification strategies, and IP reuse.
• Incentive opportunities based on individual and company performance.
• Regular employment with Shift 1 working hours in the United States of America.