Semiconductor Packaging Integration Research Manager (Advanced Packaging)

Location: Hybrid role with on-site work at hirify.global sites in Phoenix, Arizona or Portland, Oregon, United States

Annual salary: $220,920–$311,890 USD

Company

hirify.global develops semiconductor technologies and operates research and manufacturing programs for future computing platforms and customer solutions.

What you will do

• Lead advanced packaging integration research covering heterogeneous integration, chiplets, 2.5D/3DIC, hybrid bonding, wafer-level packaging, and die-to-die interconnects.
• Define integration strategies, technical roadmaps, research milestones, and decision criteria for future products, platforms, and systems.
• Manage multidisciplinary researchers, packaging technologists, process integration engineers, modeling experts, designers, and technical program leads.
• Translate system requirements into package integration solutions by balancing performance, power, area, latency, bandwidth, thermal behavior, mechanical stress, reliability, cost, and manufacturability.
• Drive feasibility studies, trade-off analysis, experiments, prototyping, reliability evaluations, failure analysis, and manufacturing feasibility reviews.
• Transfer validated research concepts to development and manufacturing by defining integration requirements, qualification gaps, process controls, risks, and scaling paths.

Requirements

• At least 7 years of experience in semiconductor technology roles, preferably in packaging integration, advanced packaging research, heterogeneous integration, process integration, or package development.
• Master’s degree in electrical engineering, mechanical engineering, materials science, chemical engineering, applied physics, microelectronics, semiconductor manufacturing, or a related discipline; a Ph.D. is preferred.
• Experience leading advanced technology research programs, multidisciplinary teams, cross-functional initiatives, or external research collaborations.
• Strong understanding of package-system integration, chiplet architectures, advanced interconnects, substrates, interposers, assembly materials, wafer-level processes, thermal-mechanical behavior, power delivery, signal integrity, reliability, and manufacturability.
• Ability to convert ambiguous integration challenges into hypotheses, experimental plans, measurable milestones, technology-readiness criteria, and recommendations.
• Strong communication skills for presenting technical findings, trade-offs, risks, and recommendations to executive, technical, and cross-functional audiences.

Nice to have

• Experience with research-to-development transfer, technology readiness frameworks, pathfinding, prototype builds, process integration learning, and early manufacturing feasibility assessment.
• Knowledge of thermal-mechanical modeling, warpage, stress, CTE mismatch, electromigration, reliability physics, high-speed I/O, power integrity, signal integrity, die-to-die interfaces, and package-level co-design.
• Patents, publications, conference presentations, industry consortia participation, university research collaboration, or external ecosystem leadership.
• Experience collaborating with suppliers, equipment vendors, universities, research labs, OSATs, foundry partners, design teams, or customer technology teams.
• Familiarity with packaging requirements for AI, HPC, data centers, automotive, mobile, networking, edge computing, advanced memory, or custom silicon.

Culture & Benefits

• Hybrid work model combining on-site work at an assigned hirify.global site with off-site work.
• Competitive pay, stock bonuses, health benefits, retirement benefits, and vacation.
• Collaboration with device, design, process, materials, reliability, modeling, test, manufacturing, university, supplier, and foundry partners.
• The role is a Position of Trust and requires consent to and successful completion of an extended background investigation.