Ph.D. Intern - Advanced Packaging & Physical Integration (Semiconductors)

Location: Santa Clara, CA, United States

Salary: $37–$73 per hour

Company

hirify.global develops semiconductor solutions and advanced packaging platforms for enterprise, cloud, AI, carrier, and high-speed connectivity infrastructure.

What you will do

• Perform signal integrity and power integrity analysis for 224G SerDes, die-to-die interconnects, and HBM interfaces.
• Develop thermal and mechanical simulation models for advanced 2.5D and 3D chiplet packages, evaluating heat dissipation, warpage, and reliability.
• Contribute to the physical design and layout of package substrates, RDL interposers, and chiplet integration schemes.
• Collaborate with chip design, assembly, and test engineering teams to validate packaging assumptions against silicon measurements and production data.
• Use Ansys, Cadence Sigrity, or equivalent EDA and simulation tools to optimize package-level electrical, thermal, and mechanical performance.
• Present analysis results and design recommendations during engineering and packaging design reviews.

Requirements

• Currently enrolled in a Ph.D. program in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.
• Research focus in advanced packaging, signal or power integrity, thermal engineering, or heterogeneous integration.
• Research or project experience in package-level SI/PI analysis, thermal-mechanical simulation, 2.5D/3D chiplet integration, substrate or interposer design, or high-speed interconnect characterization.
• Strong fundamentals in electromagnetics, heat transfer, or materials mechanics.
• Confident and independent use of Ansys HFSS, Ansys Icepak, Cadence Sigrity, or equivalent tools.
• Ability to communicate analysis results and defend design recommendations clearly.

Nice to have

• High-speed serial interface analysis at 100G per lane or above, including eye diagrams, impedance matching, crosstalk, and return loss.
• Experience with CoWoS, FOPLP, RDL interposers, or flip-chip BGA.
• Exposure to co-packaged optics, optical engine assembly, or photonic-electronic co-design.
• Power delivery network design and analysis for high-current, high-frequency applications.
• Design-for-manufacturing and reliability experience with chiplet-based multi-die packages.

Culture & Benefits

• Work on production-qualified advanced packaging platforms used in hyperscale AI infrastructure.
• Medical, dental, and vision coverage for interns.
• Paid holidays, perks and discounts, and mental health resources.
• Additional compensation may be available for Ph.D. interns.
• Access to export-controlled technology may require an export license review under U.S. regulations.

Hiring process

• Interviews evaluate individual experience, thought process, and communication skills in real time.
• AI tools, transcription apps, automated answer generators, and note-taking bots are not permitted during interviews.