Senior DFT Engineers (VLSI)

Location: Bangalore, India

Company

hirify.global provides engineering consulting services in the DFT and VLSI domain.

What you will do

• Implement and debug DFT features including BSCAN, MBIST, scan insertion, ATPG, and simulation.
• Use Cadence, Siemens Tessent, Synopsys, VCS, NCSim, or Xcelium for DFT implementation and simulation.
• Perform zero-delay and SDF timing simulations and debug issues using industry-standard simulators.
• Improve scan test coverage and work with stuck-at, transition-delay, and IDDQ fault models.
• Support SoC-level DFT, post-silicon bring-up, production activities, tester debugging, and shmoo-plot analysis.
• Collaborate with STA, physical design, customer, and cross-functional teams while guiding junior and mid-level engineers.

Requirements

• 3–15 years of hands-on experience in DFT or VLSI engineering.
• Strong understanding of BSCAN, MBIST, scan, ATPG, and simulation concepts.
• Hands-on experience in at least one major DFT area, such as MBIST, scan insertion, ATPG, or DFT simulation.
• Experience with one or more of Cadence, Siemens Tessent, and Synopsys DFT tools.
• Experience with VCS, NCSim, or Xcelium, together with strong debugging and problem-solving skills.
• B.E., B.Tech, M.E., or M.Tech in Electronics, Electrical, VLSI, or a related engineering discipline is preferred.

Nice to have

• Experience with zero-delay and SDF timing simulations.
• Experience with OCC/OPCG, EDT, and compression-logic insertion.
• Experience with post-silicon bring-up, production activities, tester debugging, and shmoo plots.
• Experience providing DFT or test-mode timing constraints to STA and physical design teams.
• Experience leading or mentoring DFT engineers.

Culture & Benefits

• Cross-functional collaboration with engineering and customer teams.
• Opportunities to lead, guide, and mentor DFT engineers.
• Full-time employment.