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3 дня назад

Package Design Staff/Sr.Staff Engineer (Semiconductor)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
India
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Package Design Staff/Sr.Staff Engineer (Semiconductor): Developing advanced microelectronic IC packages from concept through tapeout with an accent on high-speed package architecture, C4 and BGA ball maps, netlist mapping, and SI/PI optimization. Focus on defining die placement and package connectivity, validating manufacturability and reliability, and collaborating on chip, board, and system co-design.

Location: Bangalore, India

Company

hirify.global develops semiconductor solutions and advanced connectivity and compute products for enterprise, cloud, AI, and carrier architectures.

What you will do

  • Drive microelectronic package development from concept through tapeout.
  • Work with package architects and technical leads to select technologies that meet manufacturability, performance, reliability, and cost requirements.
  • Develop C4 and BGA ball maps optimized for signal integrity, power integrity, and layout efficiency.
  • Plan and validate netlist mappings across dies, interposers, and substrates, including die placement, padstacks, net assignments, and package connectivity.
  • Create and maintain Package Requirement Documents covering die arrangements, stackups, and design constraints.
  • Collaborate with chip, board, and electrical simulation teams on package and system co-design.

Requirements

  • 5–12 years of related professional experience.
  • Experience developing netlists, schematics, C4 ball maps, and BGA ball maps for large, complex, high-pin-count packages.
  • Proficiency with Cadence OrbitIO, Integrity System Planner, or equivalent design tools.
  • Strong understanding of package design rules, breakout, place and route, signal shielding, reference planes, power distribution, and pinout optimization.
  • Knowledge of SI/PI fundamentals, 2D and 2.5D packaging, CoWoS-S/R/L, EMIB, CPO, CPC, thermal and mechanical constraints, foundry design rules, and substrate manufacturing constraints.
  • Ability to collaborate across functions and global time zones, with strong communication, presentation, and documentation skills.

Nice to have

  • Experience running and interpreting signal and power simulations.
  • Experience with tool, process, and flow development, library maintenance, and basic scripting for automation.
  • Understanding of package constraints such as warpage and thermal interface materials.

Culture & Benefits

  • Participation in bonus and equity plans, including a new-hire equity grant and annual equity refreshers.
  • Competitive compensation and benefits.
  • Collaborative, transparent, and inclusive work environment.
  • Resources and support for professional growth and development.
  • Access to technology and software may be subject to U.S. export control regulations and licensing review.

Hiring process

  • Interviews assess individual experience, thought process, and communication skills.
  • AI tools, transcription applications, automated answer generators, and automated note-taking tools are prohibited during interviews.

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