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6 дней назад

Staff Engineer CPU IP Design Engineer (RISC-V)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
India
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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TL;DR
Staff Engineer CPU IP Design Engineer (RISC-V): Designing and leading RTL development for AI-enabled RISC-V vector CPU cores and matrix engines with an accent on microarchitecture, performance, power, and area optimization. Focus on developing custom CPU extensions, exploring high-performance strategies, supporting functional verification, and validating physical design requirements.

Location: Bengaluru, Karnataka, India

Company

hirify.global is a semiconductor foundry providing design, development, and fabrication services, including RISC-V CPUs and AI-enabled processors through its MIPS team.

What you will do

  • Lead RTL development for an AI-enabled RISC-V CPU core.
  • Drive the microarchitecture and design of critical CPU blocks, including vector processing and custom extensions.
  • Design an AI-enabled matrix engine to augment the vector CPU.
  • Develop and refine microarchitectural specifications from architectural exploration through detailed design.
  • Optimize RTL for power, performance, area, and timing targets.
  • Support functional verification and collaborate on physical design validation covering timing, area, reliability, testability, and power.

Requirements

  • Master’s degree with 4–7 years of experience, or PhD with 2–5 years of work experience.
  • Hands-on knowledge of pipeline stages in high-performance in-order or out-of-order CPU cores.
  • Strong microprocessor architecture knowledge, including instruction fetch and decode, branch prediction, scheduling, register renaming, reorder buffers, execution units, load/store execution, prefetching, vector datapaths, caches, and memory subsystems.
  • Knowledge of cache coherency, memory consistency, logic design, and timing and power implications.
  • Experience with SystemVerilog, Verilog, and/or VHDL, plus simulators and waveform debugging tools.
  • Role location: Bengaluru, Karnataka, India.

Nice to have

  • Experience designing RISC-V, ARM, or MIPS CPUs.
  • Experience with hardware multithreading, virtualization, SIMD, and vector- or matrix-enabled CPUs.
  • Knowledge of high-performance and low-power CPU microarchitecture techniques.
  • Experience with Perl or Python scripting.
  • Understanding of SoC-level CPU integration and safety and security microarchitecture.

Culture & Benefits

  • Inclusive and multicultural workplace.
  • Employment is subject to applicable background checks, medical screenings, and local laws.
  • Work includes compliance with environmental, health, safety, and security requirements.

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