DFT Managers (VLSI)

Location: Bangalore, India

Company

hirify.global provides consulting services for semiconductor Design-for-Test and VLSI engineering.

What you will do

• Implement and debug DFT features including MBIST insertion, scan insertion, ATPG pattern generation, and BSCAN or MBIST simulation.
• Use industry-standard DFT tools from Cadence, Siemens Tessent, and Synopsys.
• Run zero-delay and SDF timing simulations and debug issues with VCS, NCSim, or Xcelium.
• Improve scan test coverage and work with stuck-at, transition-delay, and IDDQ fault models.
• Support SoC-level DFT, post-silicon bring-up, production activities, and tester debug using shmoo plots and graphs.
• Provide test-mode timing constraints to STA and physical design teams, collaborate with customers, and mentor DFT engineers.

Requirements

• 3–15 years of hands-on experience in DFT or VLSI.
• Strong knowledge of BSCAN, MBIST, scan, ATPG, and DFT simulation concepts.
• Hands-on experience in at least one major DFT area, such as MBIST, scan insertion, ATPG, or DFT simulation.
• Experience with Cadence, Siemens Tessent, Synopsys, VCS, NCSim, or Xcelium.
• Good debugging, problem-solving, communication, and interpersonal skills.
• B.E., B.Tech, M.E., or M.Tech in Electronics, Electrical, VLSI, or a related engineering discipline is preferred.

Nice to have

• Experience with zero-delay and SDF timing simulations.
• Experience with OCC/OPCG and EDT/compression logic insertion.
• Exposure to post-silicon bring-up, production activities, tester debugging, and shmoo analysis.
• Experience providing DFT or test-mode timing constraints to STA and physical design teams.
• Experience leading or mentoring DFT engineers.

Culture & Benefits

• Full-time position with cross-functional and customer-team collaboration.
• Opportunity to lead, guide, and mentor junior and mid-level DFT engineers.