EDA Design Flow Development Engineer (Semiconductor)

TL;DR

EDA Design Flow Development Engineer (Semiconductor): Developing and maintaining transistor-level electromigration and IR drop analysis flows for custom IPs and high-performance macros with an accent on CAD methodology, automation infrastructure, and silicon correlation. Focus on enabling scalable and accurate power integrity analysis methodologies for advanced-node semiconductor designs.

Location: Must be based in the US (Santa Clara, Folsom, Hillsboro, or Austin). This role follows a hybrid work model.

Salary: $141,910–$269,100 USD

Company

hirify.global is a global leader in semiconductor design and manufacturing, driving innovation in computing and AI technology.

What you will do

• Develop and maintain transistor-level EM and IR drop analysis flows for custom IPs, SRAMs, and analog interfaces.
• Build and manage automation infrastructure for power integrity analysis and silicon correlation.
• Collaborate with circuit design, physical design, and reliability teams to enable scalable signoff methodologies.
• Implement parasitic-aware reliability modeling for advanced-node semiconductor technologies.
• Support circuit design teams in resolving power integrity challenges.

Requirements

• Bachelor's degree in Engineering or Computer Science with 6+ years of experience (or Master's with 4+ years, or PhD with 2+ years).
• Strong expertise in EM/IR reliability concepts including Electromigration and Power Drop.
• Proficiency with Redhawk and Totem tools.
• Experience with SPICE-based verification and parasitic extraction fundamentals.
• Ability to develop automation and scripts in Linux environments.
• Must be authorized to work in the United States.

Nice to have

• Deep understanding of CMOS circuit operation and power delivery networks.
• Experience with advanced-node design challenges.

Culture & Benefits

• Competitive total compensation package including base pay and stock bonuses.
• Comprehensive health, retirement, and vacation benefit programs.
• Hybrid work model allowing flexibility between on-site and off-site work.
• Opportunity to work on cutting-edge semiconductor process and packaging technology.