SOC DFT Intern - Spring 2027

Location: Austin, TX — on-site/hybrid at the Oakhill office

Company

hirify.global develops semiconductor products and technologies for digital and connected systems.

What you will do

• Support scan insertion, boundary scan, memory BIST, and other DFT implementation flows.
• Generate and validate ATPG patterns using industry-standard tools.
• Analyze test coverage and debug test patterns.
• Collaborate with RTL designers and verification teams to meet testability requirements.
• Automate DFT flows with Python, Perl, and TCL scripts.
• Document DFT methodologies, test plans, and results.

Requirements

• Currently pursuing a bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Strong understanding of digital logic design and VLSI fundamentals.
• Familiarity with Verilog or VHDL and scripting languages such as Python, Perl, or TCL.
• Strong problem-solving, attention-to-detail, communication, and teamwork skills.
• Must be returning to school or graduating at the conclusion of the Spring 2027 internship term.

Nice to have

• Exposure to scan chains, ATPG, and BIST.
• Experience with Synopsys, Cadence, or Mentor Graphics EDA tools.
• Coursework or project experience in DFT or digital IC design.
• Knowledge of STA, synthesis, RTL verification, or Linux/Unix environments.

Culture & Benefits

• Hands-on experience with industry-standard DFT tools and flows.
• Mentorship from experienced engineers in a collaborative environment.
• Exposure to the full ASIC design and test cycle.
• Opportunity to contribute to real silicon projects.