Advanced Packaging Integration and Simulation Intern (Semiconductor)

Location: Hybrid role based at an assigned hirify.global site in Phoenix, Arizona or Hillsboro, Oregon, United States, with on-site and off-site work.

Salary: $120,898–$120,902 annual target compensation for US locations.

Company

hirify.global develops semiconductor technologies and advanced packaging solutions for AI and high-performance computing.

What you will do

• Support wafer-level and package-level integration, including 2.5D/3D integration, chiplet integration, and hybrid bonding modules.
• Design and execute Design of Experiments to evaluate package architecture, process conditions, material behavior, and electrical and mechanical performance.
• Build, calibrate, and apply simulation models for package mechanics, interconnect quality, and thermal performance.
• Conduct thermo-mechanical simulations and analyze inspection, process, and simulation data to identify root causes.
• Collaborate with cross-functional engineering teams to improve process yield, reliability, manufacturability, and package performance.
• Present technical findings through reviews, presentations, and potential publications.

Requirements

• Currently pursuing a PhD in Mechanical Engineering, Materials Science and Engineering, Electrical Engineering, Physics, Manufacturing Engineering, or a closely related STEM discipline.
• Available to work full-time for the entire 3-month internship.
• At least 3 months of academic or professional experience with laboratory experimentation, engineering data analysis, simulation, process integration, or module development.
• Experience with programming or data analysis using Python, MATLAB, JMP, R, or similar tools.
• Experience with statistical analysis, Design of Experiments, or machine learning for engineering applications.

Nice to have

• Experience with advanced packaging, heterogeneous integration, wafer-level packaging, chiplet integration, or package assembly process development.
• Experience with thermal, mechanical, or electrical modeling and finite element analysis.
• Experience with failure analysis for semiconductor processes and package assembly.
• At least 6 months of relevant academic or professional experience.

Culture & Benefits

• Hands-on exposure to advanced packaging technologies for future semiconductor systems.
• Collaboration with researchers, process engineers, and modeling experts.
• Participation in technical reviews, technology forums, and intern research presentations.
• Benefits include health, retirement, and vacation programs, as well as stock bonuses and competitive compensation.

Hiring process

• Qualified applicants are evaluated based on the stated minimum and preferred qualifications.
• Specific compensation details for the preferred location and role are discussed during the hiring process.