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10 дней назад

Package Design Engineer (AI)

82 500 - 132 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
junior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Package Design Engineer (AI) (Flip-Chip BGA/ASIC): Designing complex flip-chip-BGA packages for high-performance ASICs supporting AI, networking, HPC, and 5G applications with an accent on signal integrity, power integrity, thermal performance, manufacturability, and reliability. Focus on developing critical package structures for 224G+ SerDes, ADC/DAC, DDR, and HBM, while improving design processes through automation and documentation.

Location: On-site at the hirify.global office in San Jose, California, USA, 5 days a week; this is not a remote-work position.

Annual base salary: USD 82,500–132,000, plus a discretionary annual bonus and potential equity awards.

Company

hirify.global develops semiconductor and infrastructure technology, including ASICs for artificial intelligence, networking, high-performance computing, and 5G applications.

What you will do

  • Design complex flip-chip-BGA packages for high-performance ASICs.
  • Own package design considerations including signal integrity, power integrity, manufacturability, reliability, and thermal performance.
  • Develop critical package structures for high-speed SerDes, ADC/DAC, DDR, HBM, and related interfaces.
  • Manage schedules, priorities, and deliverables across two or more projects.
  • Collaborate with internal engineers, worldwide team members, and external vendor designers.
  • Improve design-team efficiency through process development, automation, and documentation.

Requirements

  • BSEE or a similar degree with at least 2 years of flip-chip-BGA package design experience, including high-speed SerDes, or an MSEE or PhD.
  • Knowledge of electrical engineering fundamentals and package-level signal integrity and power integrity.
  • Experience with Cadence APD (Allegro Package Designer) or an equivalent layout tool.
  • Self-management and organizational skills.
  • Ability to cooperate with worldwide teams across multiple time zones and coordinate co-design with internal and external designers.
  • Physical design and layout is a foundational responsibility.

Nice to have

  • At least 1 year of experience with Cadence SKILL for Allegro or similar design-automation coding.
  • Interest in process automation and design efficiency improvements.

Culture & Benefits

  • Work as part of a worldwide R&D team.
  • Medical, dental, and vision plans.
  • 401(k) participation with company matching and an Employee Stock Purchase Program.
  • Company-paid holidays, paid sick leave, vacation time, and applicable paid family leave.
  • Employee Assistance Program and potential annual equity awards.

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