Senior Digital Design Engineer (AI Chips)

Location: Austin, Oakhill office, United States

Company

hirify.global develops semiconductor products, including automotive microprocessors, application processors, microcontrollers, networking components, and digital IP.

What you will do

• Review IP architecture, feature, programming model, microarchitecture, and interface specifications.
• Plan IP design and documentation activities, including schedule assessments and development milestones.
• Design high-quality, high-performance digital IP using Verilog and SystemVerilog RTL.
• Collaborate with verification teams on test plans and verification execution, targeting 100% coverage and NXP quality standards.
• Deliver completed IP with RTL, documentation, metrics, coverage data, defect tracking, and requirements traceability.
• Support subsystem, SoC, validation, emulation, applications engineering, and end-customer teams, including field-failure root-cause analysis and workaround identification.

Requirements

• Bachelor’s degree in electrical, computer, or computer science engineering.
• At least 4 years of experience in IP or SoC design.
• Knowledge of SoC architecture and expert knowledge of Verilog.
• Experience with design-quality checks, including lint, clock-domain-crossing analysis, and static timing analysis.
• Ability to collaborate with architecture, verification, tools, SoC front-end, validation, and applications engineering teams.

Nice to have

• Expertise in ARM AMBA bus protocol standards.
• Knowledge of functional safety and ISO 26262.
• Knowledge of CPU or cache architecture.
• Experience with C coding and scripting in Perl or Python.

Culture & Benefits

• Full-time work in the Austin Oakhill office.
• Collaboration with local and global architecture, verification, design, tools, validation, and applications teams.
• Focus on meeting committed schedules without compromising quality.
• Work centered on preventing defects from reaching silicon and improving verification methods.