Semiconductor Packaging Research Engineer (Advanced Packaging)

Location: Hybrid role based at an hirify.global site in Phoenix, Arizona, or Hillsboro, Oregon, United States, with time split between on-site and off-site work.

Annual salary: $122,440–$232,190 USD.

Company

hirify.global develops semiconductor technologies and platforms spanning AI, analytics, cloud-to-edge computing, and advanced manufacturing.

What you will do

• Research advanced packaging architectures, including chiplets, heterogeneous integration, 2.5D/3DIC, hybrid bonding, interposers, and die-to-die interconnects.
• Drive process-integration research or modeling and simulation to evaluate feasibility, reliability, manufacturability, and technology readiness.
• For process integration, define integration flows, research vehicles, design of experiments, defect and yield learning, qualification evidence, and risk-mitigation paths.
• For modeling, develop and validate thermal, thermo-mechanical, electrical, reliability, or multi-physics models using experimental and failure-analysis data.
• Translate product needs into research hypotheses, technical plans, recommendations, reports, design guidance, hirify.globallectual property, publications, and development-transfer inputs.
• Collaborate with research, design, process, materials, reliability, manufacturing, supplier, university, and ecosystem teams.

Requirements

• Master’s or Ph.D. in mechanical engineering, electrical engineering, materials science, applied physics, computational mechanics, microelectronics, semiconductor manufacturing, or a related field.
• At least 1 year of experience in semiconductor packaging research, advanced packaging integration, process integration, modeling and simulation, reliability, materials, or heterogeneous integration.
• At least 1 year of experience with process integration, research vehicle execution, design of experiments, defect and yield learning, reliability, model development and validation, or multi-physics simulation.
• At least 1 year of experience with advanced packaging technologies such as flip chip, chiplets, 2.5D/3DIC, fan-out, hybrid bonding, interposers, HBM integration, advanced substrates, or die-to-die interconnects.
• Ability to work in the hybrid model at an assigned hirify.global site in Phoenix, Arizona, or Hillsboro, Oregon.

Nice to have

• Ph.D. or deep technical specialization with 4+ years of relevant experience.
• Experience with prototype builds, technology-readiness assessment, research-to-development transfer, package-system co-optimization, or chip-package-board co-design.
• Experience with ANSYS, Abaqus, COMSOL, HFSS, Cadence, MATLAB, Python, JMP, or equivalent tools.
• Patents, publications, conference presentations, technical reports, methodology development, or competitive technology assessments.
• Ability to turn ambiguous research problems into assumptions, experiments, milestones, qualification metrics, and actionable recommendations.

Culture & Benefits

• Hybrid work model combining on-site and off-site work.
• Competitive compensation with stock bonuses.
• Health, retirement, and vacation benefits.
• Cross-functional collaboration across research, engineering, manufacturing, suppliers, universities, and the broader technology ecosystem.