FPGA Silicon Design Engineer

Location: San Jose, California, United States. Applicants must be authorized to work in the United States without employer-sponsored immigration support and meet eligibility requirements for supporting a U.S. government contract.

Salary: $149,100–$213,015 USD annually for the Bay Area California location, plus incentive opportunities.

Company

hirify.global develops programmable FPGA technologies for AI, cloud, networking, and edge markets.

What you will do

• Architect, design, and implement complex digital logic, specialized blocks, control logic, and interconnects for FPGA silicon.
• Develop and maintain production-quality Verilog and SystemVerilog RTL.
• Define and execute verification plans using UVM, constrained-random verification, SystemVerilog Assertions, simulation, and coverage-based debug.
• Support the ASIC physical design flow, including synthesis, floorplanning, placement, clock-tree synthesis, routing, static timing analysis, timing closure, and power analysis.
• Optimize performance, power, and area using industry-standard EDA tools, scripting, and automation.
• Collaborate across architecture, verification, physical design, software, firmware, and product engineering, including silicon bring-up, post-silicon debug, characterization, and root-cause analysis.

Requirements

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, plus 8+ years of FPGA or ASIC silicon design experience.
• 5+ years of experience designing complex digital logic and RTL with Verilog and/or SystemVerilog.
• 5+ years of hands-on experience with backend ASIC physical design flows, EDA tools, timing analysis, timing closure, and power analysis.
• 5+ years of experience with clock-domain crossing, reset architecture, clocking, asynchronous interfaces, finite-state machines, pipelining, and low-power design.
• 5+ years of experience with SystemVerilog, UVM, assertions, simulation, waveform analysis, coverage-based debug, and technical root-cause analysis.
• 5+ years of scripting and automation experience with Python, Perl, Tcl, Shell, or equivalent in Unix/Linux environments.

Nice to have

• Master’s or Ph.D. degree with 5+ years of ASIC or FPGA design experience.
• Experience with FPGA architecture, programmable logic resources, configuration controllers, or network-on-chip architectures.
• Experience with silicon bring-up, post-silicon validation, hardware characterization, or production readiness.
• Experience with power-intent methodologies, formal verification, linting, CDC analysis, equivalence checking, Git, or Perforce.
• Ability to mentor engineers and influence technical decisions in a cross-functional environment.

Culture & Benefits

• Regular full-time employment with incentive opportunities based on individual and company performance.
• Cross-functional collaboration across architecture, engineering, software, firmware, and product teams.
• Work focused on high-performance, power-efficient, and feature-rich FPGA products.
• Use of artificial intelligence in applicant screening, assessment, or selection.