Design Engineer II (SERDES)

Location: Bangalore, India; onsite

Company

hirify.global develops technology solutions for designing and validating electronic systems and semiconductor IP.

What you will do

• Characterize and validate analog and digital IP-based silicon solutions.
• Lead day-to-day lab testing and silicon characterization activities while managing multiple priorities.
• Develop electrical, protocol, interoperability, and compliance test suites for high-speed SERDES interfaces.
• Isolate PHY and controller features, develop calibration and compliance lab suites, and analyze test results.
• Coordinate with R&D and Marketing teams to define scope and deliver results on time.
• Develop ESD, latch-up, and HTOL tests for reliability qualification.

Requirements

• 2–10 years of experience with a BTech or 10 years with an MTech in post-silicon PHY, systems interoperability, and compliance testing.
• 5–7 years of experience managing or mentoring a small engineering team.
• Physical-layer and protocol-layer experience with at least one high-speed SERDES interface, such as Ethernet, PCIe, CXL, or UCIe.
• Experience using oscilloscopes, bit error rate testers, protocol exercisers, and analyzers, with strong debugging skills.
• Experience designing printed circuit boards at schematic and layout level, including high-speed interface design, signal integrity, and power integrity analysis.
• Expert-level knowledge of Verilog RTL coding for FPGA and proficiency in Python, C, and C++.

Nice to have

• Experience with PCIe and UCIe LTSSM states, UCIe interfaces, and Ethernet standards.

Culture & Benefits

• Full-time employment in an engineering role based in Bangalore.
• Collaboration with remote teams located worldwide.
• Opportunities to guide team members and contribute to technology-focused work.