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4 часа назад

Senior ASIC Designers (AI)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Релокация
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior ASIC Designers (AI): Designing RTL for IPs, subsystems, and SoCs supporting memory acceleration in high-performance AI and data center systems with an accent on microarchitecture, PPA optimization, and advanced ASIC design flows. Focus on defining specifications, coordinating verification and physical design, closing timing, and driving designs through tape-out.

Location: On-site in Santa Clara, California, or Boston/Cambridge, Massachusetts, United States. Relocation assistance is available to one of the office hubs.

Company

hirify.global is an early-stage startup developing memory acceleration and high-performance computing architecture for AI and modern data centers.

What you will do

  • Design RTL for IPs, subsystems, and SoCs supporting the silicon roadmap.
  • Define IP and SoC microarchitecture specifications and design methodologies.
  • Lead design reviews and optimize designs against aggressive power, performance, and area targets.
  • Coordinate with architecture, verification, physical design, firmware, DFT, and post-silicon teams to ensure system-level functionality.
  • Manage dependencies and resolve roadblocks with external IP vendors, foundries, and EDA tool providers.

Requirements

  • 5+ years of ASIC/SoC digital design experience.
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • Strong knowledge of the full ASIC/SoC lifecycle, from microarchitecture through tape-out in advanced process technologies.
  • Expertise in microarchitecture, RTL coding with Verilog/SystemVerilog, synthesis, STA/timing closure, physical design, and verification methodologies.
  • Experience optimizing PPA and integrating major subsystems such as interconnect, I/O, and memory.
  • Leadership, communication, stakeholder management, risk coordination, and the ability to work under tight schedules and budget constraints.

Nice to have

  • Design experience with Ethernet, UCIe, UALink, or similar industry standards and protocol stacks.
  • Advanced silicon device design and tape-out experience.
  • PhD in Electrical Engineering, Computer Engineering, or a related field.
  • Experience managing external design partners, IP vendors, and foundries.
  • Knowledge of design-for-testability, post-silicon debug, validation, and manufacturing test.

Culture & Benefits

  • Performance-based bonus and early-stage equity grant.
  • Employer-paid health, dental, vision, life, disability, and AD&D insurance.
  • 401(k) match with immediate vesting, financial advisors, fitness stipend, and wellness and mental health benefits.
  • 20 vacation days, 15 company holidays, and a daily lunch stipend.
  • Enterprise-level Claude and ChatGPT access, on-site parking, EV charging, and office fitness facilities or gym discounts.
  • Collaborative, continuous-learning environment focused on rigor, clarity, and high-impact AI infrastructure.

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