8 часов назад
Design Automation Engineer (Neuromorphic Computing)
122 440 - 232 190$
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Design Automation Engineer (Neuromorphic Computing) (ASIC/EDA/AI): Enhancing and maintaining Loihi's asynchronous EDA tool flow and developing automation for silicon design, verification, physical implementation, simulation, emulation, and FPGA platforms with an accent on custom low-power, high-performance designs and full ASIC lifecycle support. Focus on building production-quality automation tools and regression tests, manipulating synthesis and physical-design tools, enabling scalable software development through simulation and emulation, and applying AI-driven engineering assistants to improve tool-flow productivity.
Location: Hybrid role based at an assigned site in the United States; primary location Hillsboro, Oregon, with additional locations in Phoenix, Arizona; Folsom and Santa Clara, California; and Austin, Texas.
Annual salary range: $122,440–$232,190 USD, depending on work location, skills, experience, and education.
Company
develops semiconductor technologies and neuromorphic computing systems, including the Loihi research chip family and related physical AI solutions.
What you will do
- Enhance and maintain Loihi’s asynchronous EDA tool flow through automation algorithms, software tools, utilities, and regression tests.
- Support RTL design, verification, and physical design engineers with automated solutions for product quality and performance KPIs.
- Build scalable simulation and emulation frameworks that enable early software development against silicon designs.
- Write custom scripts to manipulate synthesis and physical design tools for low-power, high-performance designs.
- Develop capabilities spanning front-end design, physical implementation, verification, and FPGA-based emulation.
Requirements
- Bachelor’s degree with 4+ years of experience, or master’s degree with 2+ years of experience, developing and deploying production-quality silicon design tools, flows, and methods.
- 4+ years of experience developing and maintaining the ASIC tool suite, including synthesis, place and route, ATPG, FEV, RV, STA, and LVS/DRC.
- 4+ years of experience with scripting languages such as Perl, TCL, or Python.
- Experience delivering multiple silicon tape-outs for at least 2 years.
- Strong software background and familiarity with the full silicon design lifecycle.
Nice to have
- Strong SystemVerilog, SystemC, and object-oriented programming background.
- Experience with large-scale FPGA platforms such as HAPS or emulation frameworks such as ZeBu.
- 1+ year of experience using AI tools to set up tool flows, debug issues, and improve productivity.
Culture & Benefits
- Hybrid work model combining on-site work at an assigned site with off-site work.
- Competitive compensation with stock bonuses.
- Health, retirement, and vacation benefits.
- Shift 1 schedule in the United States.
Hiring process
- Recruiters can provide location-specific compensation details during the hiring process.
- follows ethical hiring practices and does not charge recruitment or medical examination fees.
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