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5 дней назад

RTL Design / Microarchitecture Engineer (ASIC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US/Taiwan
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
RTL Design / Microarchitecture Engineer (ASIC): Defining microarchitecture specifications and implementing complex digital blocks in SystemVerilog/Verilog for high-performance, scalable, and power-efficient SoC/IP designs with an accent on PPA optimization, pipelining, and ASIC/SoC integration. Focus on timing closure, verification collaboration, simulation and GLS debugging, and silicon bring-up.

Location: Taiwan, with the role based in Taipei or Hsinchu

Company

hirify.global is a semiconductor startup building high-performance and energy-efficient graphics processors for immersive content creation, simulation, and consumption.

What you will do

  • Define microarchitecture specifications from high-level architecture requirements.
  • Design and implement RTL for complex digital blocks using SystemVerilog and Verilog.
  • Optimize performance, power, and area at the RTL and microarchitecture levels.
  • Collaborate with verification teams to ensure design correctness and high coverage.
  • Integrate IP into SoC-level environments and work with physical design teams on timing closure, synthesis constraints, and floorplan-aware design.
  • Debug issues during simulation, GLS, and silicon bring-up while contributing to design reviews, documentation, and methodology improvements.

Requirements

  • Bachelor’s or Master’s degree in Electrical Engineering or a related field.
  • 5–10 years of experience in RTL design and microarchitecture.
  • Strong expertise in SystemVerilog/Verilog, microarchitecture development, performance optimization, and pipelining.
  • Experience with simulation and debugging tools such as Synopsys VCS or Cadence Xcelium.
  • Familiarity with synthesis and timing concepts, including Synopsys Design Compiler.
  • Understanding of digital design fundamentals, including FSMs, pipelines, caches, memory interfaces, and ASIC/SoC development environments.

Nice to have

  • Experience with CPU, GPU, AI/ML accelerators, networking, or high-speed data processing.
  • Knowledge of SRAM, cache hierarchies, memory subsystems, and coherency.
  • Familiarity with low-power design, formal verification, linting, GLS, SDF annotation, or silicon debug.
  • Scripting skills in Python or TCL and understanding of firmware, drivers, and hardware-software interaction.

Culture & Benefits

  • Collaborative culture built around professionalism, integrity, and respect.
  • Values include fearless experimentation, adaptability, and selfless knowledge sharing.
  • Commitment to diversity, inclusion, and equal employment opportunity.

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