Ph.D. Intern - Analog, Mixed Signal & Circuit Design

Location: Santa Clara, CA, United States; onsite

Salary: $38–$76 per hour, plus eligibility for bonus and equity plans.

Company

hirify.global develops semiconductor solutions and analog technologies that support enterprise, cloud, AI, carrier, and data infrastructure systems.

What you will do

• Design, simulate, and verify analog and mixed-signal circuit blocks from architecture and schematic through layout coordination and silicon bring-up.
• Develop production-grade IP such as high-speed SerDes blocks, Silicon Photonics drivers and receivers, ADCs, DACs, PLLs, clock networks, LDOs, and precision analog circuits.
• Use Cadence and MATLAB throughout the design process, and collaborate with layout engineers on implementation and simulation feedback.
• Participate in design reviews and present research framing, design results, decisions, and tradeoffs to the engineering team.
• Complete a structured analog design curriculum with other Ph.D. interns.

Requirements

• Currently enrolled in a Ph.D. program in Electrical Engineering or a related field, with research focused on analog, mixed-signal, or RF circuit design.
• Hands-on transistor-level experience designing and simulating analog circuit blocks such as PLLs, SerDes, ADCs, DACs, LDOs, amplifiers, or high-speed I/O.
• Strong fundamentals in device physics, noise analysis, linearity, stability, and low-power techniques in advanced CMOS processes.
• Independent experience with Cadence Virtuoso and Spectre; MATLAB or Python system-level modeling is advantageous.
• Clear communication of design decisions and tradeoffs, including presenting and defending technical work.
• Eligibility to access technology and software subject to U.S. export control laws may be required; export license review may apply.

Nice to have

• Experience with FinFET nodes such as 7nm, 5nm, or 3nm.
• Familiarity with high-speed serial links, optical transceivers, or die-to-die interconnects.
• Exposure to layout-aware design, parasitic extraction, post-layout simulation, or Verilog-A behavioral modeling.

Culture & Benefits

• Work directly with staff and distinguished engineers on production IP and research-stage silicon.
• Medical, dental, and vision coverage for interns.
• Mental health resources, paid holidays, perks, and discounts.
• Bonus and equity plan eligibility, including a new-hire equity grant and annual equity refreshers.
• Additional compensation may be available for Ph.D. interns.

Hiring process

• Technical interviews evaluate individual experience, reasoning, and communication in real time.
• AI tools, transcription applications, automated answer generators, and note-taking bots are not permitted during interviews.