Staff Modeling Architect (AI)

Location: Austin, Texas or Sunnyvale, California; full-time onsite position

Salary: $250,000–$290,000 annually, plus equity

Company

hirify.global develops silicon photonics and programmable metasurface technology for energy-efficient, high-performance AI inference hardware.

What you will do

• Bring up dense, Mixture of Experts, attention, retrieval, speech, vision, recommendation, and other inference workloads on the accelerator model stack.
• Bind Hugging Face and PyTorch workloads to the programming model and runtime so software and architecture share the same functional behavior.
• Co-design tiling, scheduling, ISA, SRAM and HBM hierarchy, NoC traffic, and multi-chip mapping across pipeline, tensor, and sequence parallelism.
• Develop Python energy, latency, performance, power, and area models, including roofline analysis and design-space exploration.
• Implement bit-accurate C++ functional models and contribute to the event-driven simulation kernel, including cycle-accurate and cycle-approximate simulation.
• Define modeling methodology for a workload area, align models with RTL through Verilator and SystemVerilog co-simulation, and mentor modeling engineers.

Requirements

• 8+ years of experience in hardware, functional, performance, or accelerator modeling and simulation.
• Strong grounding in computer architecture, microarchitecture, memory systems, and AI accelerators.
• Modern C++17 or later and Python with NumPy, Pandas, and Matplotlib.
• Experience working inside a discrete-event, cycle-approximate, or cycle-accurate simulator such as SystemC, gem5, SST, or a custom kernel.
• Ability to build LLM or accelerator workloads covering prefill, decode, MoE, GEMM tiling, and quantization.
• BS, MS, or PhD in Computer Engineering, Electrical Engineering, Computer Science, or equivalent practical experience.

Nice to have

• PhD in Computer Engineering, Electrical Engineering, or Computer Science.
• Hardware/software co-design experience with MLIR, TVM, XLA, ONNX, operator fusion, or graph compilers.
• Experience extending simulation kernels or correlating analytical models with silicon, datasheets, or measured accelerators.
• Familiarity with TLM 2.x, Verilator, SystemVerilog, DPI, UVM, HBM, DRAM controllers, cache, SRAM, NoC, AXI, DMA, and scratchpad memory.
• Power modeling with McPAT or CACTI, FPGA prototyping, or hardware emulation.

Culture & Benefits

• Work on photonics and AI hardware at an early-stage company developing energy-efficient inference technology.
• Health plan premiums are fully covered for employees and dependents, with HSA contributions.
• Unlimited PTO and flexible benefits selection.
• 401(k) matching, stock options, dental, vision, life, hospital, critical illness, and accident insurance.