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2 дня назад

Lead Vector Compute Architect (GPU)

250 000 - 350 000$
Формат работы
onsite
Тип работы
fulltime
Грейд
senior/lead
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

Текст:
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TL;DR
Lead Vector Compute Architect (GPU): Defining scalable data-parallel microarchitectures and technical direction for next-generation GPUs with an accent on performance modeling, memory systems, cache coherency, and cross-functional subsystem integration. Focus on analyzing performance, power, area, bandwidth, latency, and scalability, designing architectural test strategies, and supporting silicon bring-up and post-silicon optimization.

Location: On-site in Sunnyvale, California; candidates must be local to the Bay Area.

Salary: $250,000–$350,000 per year base pay in California.

Company

hirify.global is a semiconductor startup building high-performance and energy-efficient graphics processors for immersive content creation, simulation, and consumption.

What you will do

  • Define data-parallel microarchitectures that satisfy ISA constraints for next-generation GPUs.
  • Lead tradeoff analysis across performance, power, area, bandwidth, latency, and scalability.
  • Develop system architecture specifications, interface definitions, and microarchitecture requirements.
  • Collaborate with RTL, verification, physical design, firmware, software, and systems teams throughout development.
  • Build performance models, characterize workloads, identify bottlenecks, and optimize utilization and occupancy using C++, C, SystemC, or similar environments.
  • Define memory hierarchy, coherency architecture, and cache structures; support validation, silicon bring-up, debugging, tuning, and post-silicon optimization.

Requirements

  • 6+ years of experience in modern data-parallel microarchitecture, including workload characterization, profiling, performance modeling, out-of-order data dependency and control, and high-performance architecture design.
  • Strong understanding of data-parallel microarchitectures and subsystem integration.
  • Experience with one or more of CPU, GPU, or NPU architectures; NoC/interconnects; cache coherency protocols such as CHI, ACE, or CXL; high-speed interfaces; memory systems; or power, performance, and area optimization.
  • Strong knowledge of RTL development and verification methodologies, architecture modeling, and performance analysis tools.
  • Familiarity with firmware and software interaction in complex SoC systems.
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, along with strong problem-solving, communication, and leadership skills.

Culture & Benefits

  • First-principles approach focused on reducing barriers to content creation and consumption.
  • Values include fearless experimentation, adaptability, and selfless collaboration.
  • Medical, dental, and vision premiums fully covered.
  • Stock options and 401(k) matching.
  • Work-from-home hardware provided.
  • Commitment to a diverse, inclusive, professional, and respectful workplace.

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