Назад
Company hidden
12 дней назад

Senior FPGA Design Engineer (Optical Networking)

150 000 - 170 000CAD
Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
Canada
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
Для мэтча и отклика нужен Plus

Мэтч & Сопровод

Для мэтча с этой вакансией нужен Plus

Описание вакансии

Текст:
/
TL;DR
Senior FPGA Design Engineer (SystemVerilog/Optical Networking): Designing and implementing FPGA logic for advanced, high-speed optical networking and photonics products with an accent on clock domain crossings, synthesis flows, timing constraints, and timing closure. Focus on analyzing implementation reports, resolving timing and resource challenges, and developing production-quality designs with hardware, verification, and systems teams.

Location: Ottawa, ON, Canada; full-time and on-site at the client's Ottawa office

Salary: CAD 150,000–170,000 per year, plus bonus and benefits.

Company

hirify.global supports electronic design teams across Canada and internationally, specializing in ASIC and FPGA design, verification, and embedded software development.

What you will do

  • Design and implement FPGA logic in SystemVerilog from micro-architecture through timing-clean implementation.
  • Analyze and handle clock domain crossings, including synchronization strategies and CDC verification.
  • Own synthesis flows, configure tool settings, develop timing constraints, and drive designs to timing closure.
  • Analyze synthesis and timing reports to resolve timing, congestion, and resource issues.
  • Collaborate with hardware, verification, and systems teams to deliver robust, testable, production-quality designs.
  • Contribute to design reviews, documentation, and improvements to FPGA design practices.

Requirements

  • Approximately 10–15 years of hands-on FPGA design experience.
  • Strong, current expertise in SystemVerilog.
  • Practical experience identifying and handling clock domain crossings.
  • Hands-on experience configuring synthesis tool settings and developing SDC timing constraints.
  • Ability to analyze synthesis tool reports and act on the findings.
  • Availability to work full-time and on-site at the client's Ottawa location.

Nice to have

  • Exposure to UVM-based verification.
  • Tcl or Python scripting skills for automating design flows.
  • Familiarity with high-speed interfaces used in optical and networking products.

Culture & Benefits

  • Challenging technical work with technology and innovation leaders.
  • Stable, long-term client engagement with opportunities to build deep ownership of delivered designs.
  • Supportive environment where engineers are trusted, valued, and engaged.
  • Emphasis on work-life balance.
  • Bonus and benefits included in the compensation package.

Hiring process

  • Client and program details are shared confidentially during the interview process.
  • Only candidates selected for an interview will be contacted.

Будьте осторожны: если работодатель просит войти в их систему, используя iCloud/Google, прислать код/пароль, запустить код/ПО, не делайте этого - это мошенники. Обязательно жмите "Пожаловаться" или пишите в поддержку. Подробнее в гайде →