9 часов назад
Design Engineer - STA
109 700 - 175 500$
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Design Engineer - STA (ASIC/Static Timing Analysis): Developing and signing off timing environments for high-performance custom CMOS ASICs and SoCs in advanced process nodes, with an accent on multi-mode multi-corner analysis, timing constraints, and closure across PVT corners. Focus on automating timing flows, debugging signal integrity and clock network issues, and driving timing convergence with physical design, synthesis, and clock teams.
Location: Fort Collins, Colorado, USA; onsite at 4380 Ziegler Road
Annual base salary: USD 109,700–175,500, plus discretionary annual bonus and equity awards.
Company
's ASIC Products Division develops custom CMOS ASICs for AI, cellular, networking, computing, and storage products.
What you will do
- Develop, validate, and maintain timing constraints for complex SoC designs across multiple modes and process corners.
- Perform static timing analysis using Synopsys PrimeTime and/or Cadence Tempus.
- Define timing signoff methodologies and execute pre- and post-route analysis, QoR evaluations, and closure verification.
- Generate and validate timing ECOs to achieve signoff-quality closure across PVT corners.
- Automate timing flows and analysis with Tcl and scripting languages such as Python or Perl.
- Collaborate with physical design, synthesis, and clock teams to debug timing violations, signal integrity issues, and clock network challenges.
Requirements
- BS in Electrical or Computer Engineering with 8+ years of relevant experience, or MS with 6+ years.
- Deep understanding of VLSI design principles and ASIC physical design fundamentals.
- Experience with timing constraints, setup/hold analysis, MMMC timing, ECO convergence, and timing signoff.
- Knowledge of PLLs, clock networks, flip-flops, latches, memories, RC networks, crosstalk, and noise analysis.
- Understanding of advanced STA techniques including POCV, SOCV, LVF, PBA, and SPICE correlation, as well as CCS, ECSM, and NLDM timing libraries.
- Strong Tcl and Linux/UNIX experience; Python, Perl, or Ruby proficiency is preferred.
Culture & Benefits
- Work with cross-functional and global design teams and external customers.
- Opportunity to provide technical leadership, mentor colleagues, and improve design methodologies.
- Medical, dental, and vision plans.
- 401(k) participation with company matching and an Employee Stock Purchase Program.
- Paid holidays, sick leave, vacation time, family leave, and other applicable leaves of absence.
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