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5 дней назад

Senior ASIC Design Engineer (AI/HPC Networking)

Формат работы
remote (только USA)
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
US
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior ASIC Design Engineer (AI/HPC Networking): Building high-speed ASIC and SoC designs for AI and high-performance computing networking with an accent on RTL implementation, packet processing, and Ethernet-based interconnects. Focus on timing closure, multi-clock-domain interfaces, post-silicon validation, and debugging Host Fabric Interface subsystems for scalable compute clusters.

Location: Remote within the United States; department location listed as San Jose, California.

Company

hirify.global develops high-performance scale-out networking solutions combining hardware, software, and system technologies for AI and HPC datacenters.

What you will do

  • Implement RTL designs using Verilog and SystemVerilog for high-speed data paths and packet-processing logic.
  • Collaborate with verification engineers on block- and system-level test plans and design coverage.
  • Define timing constraints and work with Physical Design engineers on timing closure.
  • Support post-silicon validation and debug ASIC issues with hardware, firmware, and software teams.
  • Optimize performance and power-aware design strategies for Host Fabric Interface subsystems.

Requirements

  • B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field.
  • 8+ years of post-college digital design experience with Verilog and SystemVerilog.
  • Experience designing ASIC RTL for high-speed data paths or packet processing.
  • Deep understanding of Host Ethernet adaptor architectures.
  • Familiarity with timing closure, modern physical design methodologies, system-level debugging, and root cause analysis.
  • Strong verbal and written communication skills.

Nice to have

  • Knowledge of Ethernet architecture and networking protocols, including TCP/IP, RDMA/RoCE, and IPSec.
  • RTL development experience for Ethernet host adapters and system debugging.
  • Experience with multiple clock domains and asynchronous interfaces.
  • 5+ years of scripting experience with TCL, Python, or Perl.
  • Familiarity with Design Compiler, Spyglass, or PrimeTime.

Culture & Benefits

  • Flexible remote work environment within the United States.
  • Compensation includes equity, cash, and performance-based incentives.
  • Medical, dental, vision, disability, and life insurance coverage.
  • 401(k) with company match, paid holidays, sick time, bonding leave, and pregnancy disability leave.
  • Additional benefits include dependent care FSA, accidental injury insurance, pet insurance, and Open Time Off for eligible regular full-time exempt employees.

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