обновлено 4 дня назад
Internship - Hardware Robustness for SMI Register Interfaces in Automotive PHY Chips
Вакансия из Hirify Global, списка международных tech-компанийДля мэтча и отклика нужен Plus
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Internship - Hardware Robustness for SMI Register Interfaces in Automotive PHY Chips (SystemVerilog/MDIO): Investigating and prototyping hardware mechanisms to detect or correct bit errors on SMI buses or within on-chip register files, with an accent on RTL design and automotive communication interfaces. Focus on developing protocol wrappers and register-file architectures, fault-injection verification, and coverage-driven testbench methodology.
Location: Eindhoven, Netherlands; hybrid
Company
develops semiconductor solutions, including automotive PHY chips with SMI register interfaces.
What you will do
- Investigate hardware-based mechanisms for detecting or correcting bit errors on the SMI bus or within the on-chip register file.
- Prototype transparent robustness mechanisms that reduce reliance on software read-back and redundancy checks.
- Design digital RTL components in SystemVerilog, including FSMs, protocol wrappers, and register-file architectures.
- Develop fault-injection verification environments and apply coverage-driven testbench methodology.
- Participate in code reviews and use professional chip-design and EDA workflows.
Requirements
- Final-year BSc student in Electrical Engineering, Microelectronics, Embedded Systems, or Computer Engineering.
- Basic knowledge of digital logic design.
- Familiarity with at least one HDL: Verilog, SystemVerilog, or VHDL.
- Analytical and structured approach to trade-off problems.
- Comfortable reading technical English.
Culture & Benefits
- Six-month full-time internship.
- Exposure to silicon-level SMI/MDIO protocol internals.
- Experience with professional chip-design workflows, code reviews, and EDA tools.
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