Software Engineer – High-Speed SerDes (AI)

Location: Saratoga, California, United States

Company

hirify.global is a Silicon Valley hardware startup developing silicon, packaging, software, and systems that accelerate AI data-center infrastructure.

What you will do

• Develop embedded software and firmware for configuring, initializing, calibrating, monitoring, and optimizing high-speed SerDes PHYs.
• Lead bring-up of 224G PAM4 Ethernet SerDes and develop support for PCIe and UCIe interfaces, including link training, lane management, repair, recovery, and diagnostics.
• Implement adaptation and calibration workflows covering transmitter and receiver equalization, eye optimization, margining, skew management, lane remapping, and environmental compensation.
• Build APIs, drivers, firmware interfaces, command-line tools, diagnostic utilities, and automated characterization and production-test software.
• Analyze link failures across silicon, package, board, connector, cable, and optical channels using laboratory measurements and simulation results.
• Define reusable SerDes software abstractions, technical specifications, validation plans, and debug procedures while mentoring engineers.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Typically 10 or more years of experience in SerDes firmware, PHY software, silicon bring-up, or high-speed interface validation.
• Deep understanding of PAM4 and NRZ signaling, channel loss, jitter, noise, crosstalk, clock and data recovery, equalization, BER, eye diagrams, link margin, and forward error correction.
• Hands-on experience bringing up an advanced SerDes generation, preferably 112G or 224G PAM4, and experience with Ethernet, PCIe, UCIe, or comparable high-speed interfaces.
• Strong C and C++ programming skills, plus Python or a similar language for automation, characterization, data analysis, and laboratory equipment control.
• Experience with SerDes register interfaces, embedded processors, real-time firmware, pre- and post-silicon debugging, signal-integrity analysis, and laboratory equipment such as oscilloscopes, BERTs, VNAs, and protocol analyzers.

Nice to have

• Experience with 224G Ethernet PHYs, 800G or higher-speed Ethernet, PCIe 6.x or 7.0, and UCIe chiplet systems.
• Experience integrating third-party SerDes IP, developing vendor-independent abstraction layers, or working with advanced packaging and chiplet architectures.
• Knowledge of CMIS, pluggable optics, retimers, active electrical cables, linear-drive optics, and relevant IEEE, PCI-SIG, and UCIe specifications.
• Experience with power optimization, fast link recovery, production screening, yield analysis, manufacturing tests, and field diagnostics.

Culture & Benefits

• Work with an experienced engineering organization spanning silicon, packaging, optics, software, and systems.
• Contribute to AI infrastructure technology designed to improve performance, GPU utilization, power efficiency, cost, and reliability.
• Join a company funded with more than $200 million, including an oversubscribed Series A round.
• The starting base salary is determined based on skills, experience, qualifications, work location, market trends, and comparable employee compensation.