Senior Serdes System Design Engineer/Architect (Serdes)

Location: USA-TX-Austin - River Place B7

Annual base salary: USD 121,900–195,000, plus discretionary annual bonus and equity awards.

Company

hirify.global develops high-speed Serdes products within its Physical Layer Products Division.

What you will do

• Develop channel models and system-level simulations to define high-speed 100G+ Serdes architectures.
• Define signal-processing block requirements, architectures, and laboratory test plans.
• Build bit-exact MATLAB and C/C++ system models for simulation and verification.
• Collaborate with analog and digital designers on implementation in advanced silicon technology nodes.
• Perform RTL vector-matching verification, firmware development, lab testing, and debugging.
• Support wireline standards development, documentation, customer meetings, and application collateral.

Requirements

• B.S.E.E. with 8+ years of relevant experience or M.S.E.E. with 6+ years of relevant experience.
• Expert knowledge of communication theory and digital signal-processing algorithms.
• Working knowledge of analog circuit behavior, transmission-line theory, and S-parameters.
• Expert proficiency in MATLAB and C/C++ programming.
• Hands-on laboratory testing and debugging skills.
• Experience with high-speed CDR PLL design, wireline equalization, RTL coding, or IEEE 802.3/OIF and PCIe Serdes standards is advantageous.

Culture & Benefits

• Full-time employment in a team of communication-system and mixed-signal ASIC experts.
• Medical, dental, and vision plans.
• 401(k) participation with company matching and an Employee Stock Purchase Program.
• Paid holidays, sick leave, vacation, and applicable family and other leaves.
• Employee Assistance Program, annual bonus eligibility, and equity opportunities.