12 дней назад
Staff / Senior Staff Physical Design Engineer
200 000 - 220 000$
Мэтч & Сопровод
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Описание вакансии
Текст:
TL;DR
Staff / Senior Staff Physical Design Engineer (ASIC physical design): Driving full-chip or block-level physical implementation from netlist to GDSII with an accent on timing closure, power, area, and signoff quality. Focus on floorplanning, placement, CTS, routing, advanced STA across PVT corners, physical verification, ECOs, and automation with Python/TCL.
Location: Sunnyvale, California; on-site in the office 5 days a week. No hybrid option is available.
Salary: $200,000–$220,000 per year in California.
Company
is a semiconductor startup building high-performance, energy-efficient graphics processors for immersive content creation, simulation, and consumption.
What you will do
- Own the end-to-end physical design flow from synthesis support and floorplanning through placement, CTS, routing, and signoff.
- Drive setup and hold timing closure across multiple PVT corners using OCV and POCV methodologies.
- Debug DRC, LVS, EM, and IR issues and drive clean signoff and tapeouts.
- Optimize designs for power, performance, and area while integrating SRAM, IO, and analog hard macros.
- Manage ECO flows, GLS, SDF generation, and timing-related debug.
- Develop automation scripts in Python and TCL and collaborate with RTL, architecture, verification, foundry, and vendor teams.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering or a related field.
- 8–12 years of ASIC physical design experience, including full-chip or large-block implementation and tapeouts.
- Strong expertise in floorplanning, power planning, placement, CTS, routing, physical verification, STA, and timing closure.
- Hands-on experience with Synopsys ICC2, Cadence Innovus, Synopsys PrimeTime, and Mentor Calibre.
- Experience with advanced nodes, preferably 7nm and below, plus strong debugging and problem-solving skills.
- Ability to work on-site in Sunnyvale, California 5 days per week.
Nice to have
- Low-power design experience with UPF or CPF and familiarity with multi-voltage designs and power domains.
- EMIR analysis experience, such as with Ansys RedHawk-SC.
- Experience with high-speed interfaces or complex CPU, GPU, or AI SoCs.
- Exposure to GLS and timing-related silicon debug.
Culture & Benefits
- Medical, dental, and vision premiums covered at 100%.
- Stock options and a 401(k) match.
- WFH hardware provided.
- Culture centered on professionalism, integrity, respect, fearlessness, adaptability, and collaborative learning.
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