ECC Design Engineering Intern (Verilog/SystemVerilog)

Location: San Jose, United States; 100% onsite for 6 months

Salary: $35–$45 per hour

Company

hirify.global develops advanced DRAM, NAND flash, and semiconductor memory solutions for mobile devices, data centers, and IT infrastructure.

What you will do

• Run FPGA systems and collect performance data.
• Manage design databases in Git.
• Code RTL logic using Verilog.
• Run Synopsys VCS simulations and debug compilation, hangs, and functional failures.
• Collaborate with designers, verification engineers, and other teams to identify correct solutions.

Requirements

• Completed or in-progress BS/MS degree in Electrical Engineering, Computer Engineering, or a related field.
• Proficiency in Verilog and SystemVerilog.
• Laboratory experience with Windows software and hardware and FPGA systems.
• Good communication skills and reliable work ethic.
• Availability for 40 hours per week, Monday through Friday, and a 100% onsite commitment for the 6-month internship.

Nice to have

• Understanding of the ASIC/FPGA workflow from concept to real silicon.
• Scripting experience with Python, Perl, or Tcl.
• Experience with LDPC or algebraic codes such as BCH/RS.
• Problem-solving mindset.

Culture & Benefits

• Six-month internship focused on advanced ECC IP development for enterprise SSDs.
• Full-time schedule of 40 hours per week.
• Opportunity to contribute to semiconductor memory technologies used in mobile and cloud computing.