10 часов назад
Staff Engineer, DRAM
163 000 - 253 000$
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Staff Engineer, DRAM (DRAM/HBM): Designing and optimizing next-generation DRAM architectures, floorplans, test modes, DFT methodologies, and power delivery networks with an accent on full-chip simulation, reliability, performance analysis, and mass-production optimization. Focus on developing HBM products, analyzing silicon electrical data, reducing power consumption, and coordinating architecture and verification work across cross-functional engineering teams.
Location: Daily onsite presence at the San Jose office, United States
Base pay range: $163,000–$253,000 USD per year, plus incentive opportunities.
Company
develops memory and semiconductor technology for smartphones, electric vehicles, hyperscale data centers, IoT devices, and other applications.
What you will do
- Develop DRAM architecture, optimize floorplans, and define requirements for next-generation memory products.
- Lead design specifications, performance analysis, test plans, and technical interactions with internal and external customers.
- Design ROW, column, and bank architectures with related test modes, while developing methods to reduce DRAM power consumption.
- Develop and implement DFT architecture and methodology, including full-chip simulation and functional verification.
- Plan and optimize power delivery networks and analyze silicon electrical data to validate new core architectures.
- Collaborate with product, process integration, quality assurance, product engineering, modeling, and marketing teams.
Requirements
- Bachelor’s degree with 10+ years of relevant industry experience, Master’s degree with 8+ years, or PhD with 5+ years of experience in DRAM or a related technical field.
- Required knowledge and demonstrated achievements in memory design.
- Proficiency with design software and statistical analysis tools.
- Experience with DRAM product development, including DDRx, GDDRx, LPDDRx, or HBMx.
- Strong knowledge of DRAM I/O interfaces, SERDES, and full-chip functional verification.
- Understanding of ASIC design flow, including RTL design, verification, logic synthesis, and timing analysis.
Nice to have
- Demonstrated innovation and creativity in solving complex design problems.
- Curiosity, resilience, adaptability, and collaborative communication across diverse teams.
Culture & Benefits
- Flexible work environment aligned with the onsite office policy.
- Medical, dental, vision, and 401(k) benefits.
- 4+ weeks of paid time off annually, plus holidays and sick leave.
- Family support benefits, including fertility care, adoption, and medical travel assistance.
- Emotional wellness resources, onsite café and gym, virtual fitness classes, and charitable giving match.
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