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11 дней назад

Senior Principal Engineer - Switch Architecture (ASIC)

Формат работы
onsite
Тип работы
fulltime
Грейд
senior
Английский
b2
Страна
India
Вакансия из списка Hirify.GlobalВакансия из Hirify Global, списка международных tech-компаний
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Описание вакансии

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TL;DR
Senior Principal Engineer - Switch Architecture (ASIC): Defining and validating next-generation data center switch ASIC architectures with an accent on behavioral and performance modeling, feature and protocol definition, and cross-functional technical leadership. Focus on analyzing latency, throughput, memory, power, area, and QoS tradeoffs, engaging with silicon implementation and bring-up, and shaping scalable architectures for cloud and AI data centers.

Location: Bangalore, India; on-site collaboration required

Company

hirify.global develops semiconductor solutions for enterprise, cloud, AI, carrier, optical interconnect, and custom silicon infrastructure.

What you will do

  • Define product architectures, features, pipelines, and protocols for next-generation data center switch ASICs.
  • Develop behavioral and performance models to validate architectural decisions and scalability.
  • Drive switch architecture from high-level concepts through micro-architecture engagement, silicon bring-up, and production.
  • Analyze latency, throughput, memory architecture, power, area, and QoS tradeoffs.
  • Collaborate with ASIC design, software, SerDes, firmware, validation, systems engineering, product, and customer teams.
  • Contribute to roadmap planning, customer and standards-body discussions, and mentor engineers.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related field with 15+ years of relevant experience, or a Master’s/PhD with 10–12+ years of semiconductor architecture or ASIC development experience.
  • Strong experience designing or architecting complex ASICs, ideally for networking or switching.
  • Expertise in behavioral and performance modeling, architectural validation, and system-level tradeoff analysis.
  • Strong programming skills in C/C++ and Python.
  • Ability to collaborate across geographies and multidisciplinary engineering teams and communicate complex architectural concepts clearly.
  • Eligibility to access export-controlled technology and software is required; applicants may be subject to an export license review.

Nice to have

  • Experience with multi-die or chiplet architectures, die-to-die interfaces, or advanced packaging.
  • Familiarity with switch pipelines, buffer management, traffic engineering, and programmable datapaths.
  • Experience working with customers or standards bodies.
  • Published papers, patents, or prior leadership experience in architecture teams.

Culture & Benefits

  • Collaborative on-site engineering culture with daily in-person collaboration.
  • Opportunity to shape switch silicon deployed in hyperscale cloud and AI data centers.
  • Cross-domain work spanning hardware, software, systems, and customer engineering.
  • Bonus and equity plan eligibility, including a new-hire equity grant and annual equity refreshers.
  • Competitive compensation and benefits in a stable global semiconductor organization.

Hiring process

  • Interviews assess individual experience, technical reasoning, and communication skills in real time.
  • Use of AI tools, transcription apps, automated answer generators, or note-taking bots during interviews is prohibited and may result in disqualification.

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