Staff Layout Engineer (IC Layout)

Location: Singapore-Yishun; must be available to relocate to Singapore immediately

Company

hirify.global's Library Group, part of the Central Engineering Group, develops circuit layouts for memory, I/O, and standard-cell libraries.

What you will do

• Apply layout guidelines, new process rules, and technical requirements for standard-cell, memory, and I/O libraries.
• Plan schedules and develop layout floor plans.
• Complete quality layout and physical verification within planned timelines.
• Adapt quickly to new methodologies and collaborate across the library team.
• Lead technology reviews and document layout methodologies, flows, and guidelines.
• Lead or train junior engineers.

Requirements

• At least 8 years of strong IC layout experience.
• Experience with Cadence Layout, Cadence schematic capture, Virtuoso XL/VXL/EXL, Calibre, and Hercules.
• Experience with submicron processes such as 16nm, 7nm, 5nm, 2nm, A14, and below.
• Experience in digital layout for standard cells, memory, and I/O, including floor-planning, hierarchical layout, and chip integration.
• Strong memory layout and physical verification experience, including LVS, DRC, ERC, antenna, and electromigration checks in CMOS processes.
• Ability to work independently and collaboratively, with leadership skills in project management.

Nice to have

• Analog layout experience.
• Memory compiler experience.
• Script programming and SKILL programming knowledge.
• Strong knowledge of memory layout topology.

Culture & Benefits

• Full-time position in the Library Group.
• Work involves collaboration, independent execution, and communication within the library team.
• hirify.global is an equal opportunity employer.