Silicon Integration Design Engineer - Timing Model (FPGA)

Location: Penang, Malaysia; right to work in Malaysia required

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Collaborate with IP designers, modeling specialists, and software teams to align timing model requirements with FPGA tool specifications.
• Define timing arcs and constraints from IP functionality and specifications.
• Perform quality checks, resolve missing timing arcs and clock information, and generate timing reference models.
• Compare proprietary timing models with Liberty format (.lib) models.
• Run custom design and SPICE simulations to construct proprietary timing models.
• Generate full-chip timing models using SPICE simulations or static timing analysis reports.

Requirements

• 10 years of hardware integration design experience.
• Experience taking at least two products through the complete development cycle to tape-out.
• Proficiency in schematic generation with Cadence Virtuoso and SPICE simulation.
• Working knowledge of SystemVerilog, synthesis, static timing analysis, floor-planning, power estimation, timing, and back-end methodologies.
• Experience with Linux scripting and Python.
• Successful background and reference checks, plus satisfactory proof of the right to work in Malaysia.

Nice to have

• FPGA timing model and power model expertise.
• Experience with PrimeTime or Liberate.
• Experience and knowledge of place-and-route.

Culture & Benefits

• Results-oriented, fast-paced, and team-first working environment.
• Focus on R&D, product innovation, and customer service.
• Comprehensive compensation and benefits program.
• Inclusive workplace valuing diverse individuals, ideas, perspectives, and insights.
• Opportunity to use AI tools for content creation and large-dataset analysis.