SoC Frontend Integration Engineer (FPGA)

Location: Penang, Malaysia

Company

hirify.global is expanding a team responsible for frontend integration of complex SoC FPGA designs.

What you will do

• Construct top-level SoC RTL integrations by assembling internal and third-party IPs.
• Own SoC hierarchy, connectivity, scalability, and frontend quality closure.
• Enable SoC-level simulation, emulation, regression, and Quartus integration with verification and software teams.
• Provide frontend handoffs for physical integration, timing and power convergence, pinout development, and reliability assessments.
• Debug integration issues across RTL, verification, and downstream flows.
• Review IP deliverables and improve interfaces, clocking, reset, power requirements, automation, and documentation.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience with RTL design and integration using Verilog and SystemVerilog.
• Experience with frontend quality checks including lint, CDC, RDC, logical verification compilation, and emulation.
• Solid understanding of SoC architectures and IP-based design methodologies.
• Comfort working in Linux and using Perl, Python, Tcl, or Shell scripting.
• Strong debugging, problem-solving, and cross-functional communication skills.

Nice to have

• Knowledge of AI/ML SoC applications for improving SoC integration productivity.

Culture & Benefits

• Regular full-time position.
• Shift 1 schedule in Malaysia.
• Cross-functional collaboration across architecture, IP design, verification, reliability, timing and power, physical design, software, and post-silicon teams.