13 дней назад
Principal Mask Design Engineer (Memory Technology)
Мэтч & Сопровод
Для мэтча с этой вакансией нужен Plus
Описание вакансии
Текст:
TL;DR
Principal Mask Design Engineer (Memory Technology): Leading mask layout design for peripheral circuits and coordinating global teams to enable successful tape-outs with an accent on STD/block layout, SA-RD layout, signal and power planning, floor planning, and full-chip integration. Focus on layout verification with Calibre DRC and Synopsys LVS, maintaining design quality and schedules, and mentoring junior engineers.
Location: Seoul Office, Seoul, South Korea
Company
develops and manufactures Flash memory and advanced memory technology solutions for global data needs.
What you will do
- Lead mask layout design for peripheral circuits in memory technology.
- Develop STD/block layouts, SA-RD layouts, signal and power plans, and floor plans.
- Drive full-chip integration and coordinate with global teams to enable successful tape-outs.
- Perform layout verification and maintain design quality and project schedules.
- Improve team capabilities and layout quality through technical guidance and mentorship.
Requirements
- 10+ years of experience in IC layout.
- Experience with Virtuoso Layout Editor.
- Experience with Calibre DRC.
- Experience with Synopsys LVS.
- Strong mask layout design, verification, and technical leadership capabilities.
Nice to have
- English skills.
- Knowledge of layout automation.
- Experience managing or leading teams.
Culture & Benefits
- Inclusive environment focused on diversity, belonging, respect, and contribution.
- Support and accommodations are available for applicants with disabilities throughout the hiring process.
- Work with global teams on advanced memory technology and manufacturing projects.
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