Integration Design Engineer - Power Model

Location: Penang, Malaysia; right to work in Malaysia required

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power-management devices.

What you will do

• Collaborate with IP designers to plan power-number generation and power-model development for custom layout and ASIC IP.
• Develop power models covering multiple IPs and operating modes using schematic design, SPICE simulation, Liberty files, and power reports.
• Define vector-based and vectorless power-estimation methodologies according to software requirements.
• Use FPGA tools to calculate power and derive subsystem- and IP-level models.
• Quality-check and consolidate models for software consumption, power calculators, and estimation workflows.
• Correlate simulation-based models with silicon data to improve estimation accuracy and customer outcomes.

Requirements

• 10 years of hardware integration design experience, including development through tape-out.
• Experience correlating silicon data with simulation data.
• Proficiency in schematic generation with Cadence Virtuoso and SPICE simulation.
• Familiarity with floor planning, power estimation, timing, and back-end methodologies.
• Experience with Linux scripting and Python.
• Strong written and oral communication skills and the ability to stay current with technology and design advances.

Nice to have

• FPGA power modeling and FPGA tool usage for power estimation.
• Working knowledge of PTPX, Totem, or Voltus.
• Experience using AI tools to accelerate content creation and analyze large datasets for patterns.

Culture & Benefits

• Fast-paced, results-oriented, team-first working environment.
• International organization focused on R&D, product innovation, and customer service.
• Comprehensive compensation and benefits program.
• Background and reference checks are required.