Senior Soft IP Design Engineer (FPGA)

Location: Penang, Malaysia. The role requires satisfactory proof of the right to work in Malaysia.

Company

hirify.global develops low-cost, low-power programmable logic solutions, including FPGA, CPLD, and programmable power management devices.

What you will do

• Build Connectivity IP portfolios for Lattice FPGA solutions.
• Work closely with architects to translate specifications into high-speed RTL designs.
• Optimize designs for performance, power consumption, and logic utilization.
• Perform FPGA RTL design, CDC and lint analysis, verification, debugging, and timing closure.
• Conduct hardware validation and hardware interoperability testing.
• Develop soft IP packages, example designs, and testbenches.

Requirements

• BS, MS, or PhD in Electronics or Computer Engineering.
• At least 7 years of FPGA IP design experience.
• Programming experience with Verilog, SystemVerilog, C/C++, Perl, TCL, or Python.
• Ability to work independently and execute effectively in dynamic and uncertain environments.
• Right to work in Malaysia is required.

Nice to have

• Experience with high-speed SERDES and video protocols such as DisplayPort, HDMI, MIPI, or SDI.
• Experience with SPI, I2C, or I3C peripherals.
• Experience in soft IP packaging, example design, and testbench development.

Culture & Benefits

• Work in an international organization focused on R&D, product innovation, and customer service.
• Collaborate within a team-first, results-oriented environment.
• Access a comprehensive compensation and benefits program.
• Work alongside a global workforce of engineers, designers, manufacturing specialists, and customer-facing teams.