ASIC Design Engineer Intern (AI)

Location: US Headquarters

Company

hirify.global develops AI vision processors for edge applications that extract data from high-resolution video streams.

What you will do

• Design and implement video compression, image processing, neural network accelerator, and processor-core logic.
• Develop and verify RTL using Verilog and SystemVerilog.
• Synthesize and optimize RTL for timing, area, and power.
• Build unit- and cluster-level testbenches, BFMs, random test generators, and functional coverage monitors.
• Create test plans and execute random and directed verification cases.
• Contribute to front-end methodologies, tool flows, chip bring-up, and testing.

Requirements

• Master’s degree in Electrical, Electronics, or Computer Engineering.
• 0–5 years of experience.
• Understanding of computer architecture, logic design, and VLSI design.
• Knowledge of Verilog, SystemVerilog, Perl, design verification, and functional coverage.
• Ability to write scripts and assembly language programs.
• Knowledge of logic synthesis and timing closure, with strong communication and teamwork skills.

Culture & Benefits

• Full-time internship position.
• Collaborative work requiring strong communication and teamwork.
• Hands-on participation in chip bring-up and testing.